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2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
This patch does several things. First, the counter for fully busy cycles for a controller is now kept with in the controller, instead of being part of the profiler. Second, the topology class no longer keeps an array of controllers which was only used for printing stats. Instead, ruby system will now ask each controller to print the stats. Thirdly, the statistical variable for recording how many different types were created is being moved in to the controller from the profiler. Note that for printing, the profiler will collate results from different controllers.
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
Prior to this changeset, we used to clear sys.argv before entering the IPython shell. This caused some versions of IPython to crash because they assume argv[0] to exist. The correct way of overriding the arguments passed to IPython is to set the argv keyword argument when initializing the shell.
2013-02-10config: Don't call sys.exit in interactive mode in run()Andreas Sandberg
The run() method in Simulation.py used to call sys.exit() when the simulator exits. This is undesirable when user has requested the simulator to be run in interactive mode since it causes the simulator to exit rather than entering the interactive Python environment.
2013-01-31sim: remove unused struct priority_compareNilay Vaish
2013-01-31ruby: correct computation of number of bits required for addressNilay Vaish
The number of bits required for an address was set to floorLog2(memory size). This is correct under the assumption that the memory size is a power of 2, which is not always true. Hence, floorLog2 is being replaced with ceilLog2.
2013-01-31mem: Add comments for the DRAM address decodingAndreas Hansson
This patch adds more verbose comments to explain the two different address mapping schemes of the DRAM controller.
2013-01-31stats: Update stats for regressions using SimpleDDR3Andreas Hansson
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
This patch adds two additional scheduling constraints to the DRAM controller model, to constrain the activation rate. The two metrics are determine the size of the activation window in terms of the number of activates and the minimum time required for that number of activates. This maps to current DDRx, LPDDRx and WIOx standards that have either tFAW (4 activate window) or tTAW (2 activate window) scheduling constraints.
2013-01-31mem: Separate out the different cases for DRAM bus busy timeAndreas Hansson
This patch changes how the data bus busy time is calculated such that it is delayed to the actual scheduling time of the request as opposed to being done as soon as possible. This patch changes a bunch of statistics, and the stats update is bundled together with the introruction of tFAW/tTAW and the named DRAM configurations like DDR3 and LPDDR2.
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
the cache drainManager is set but never cleared, this is because the cache itself does not need to be drained and thus never triggers a signalDrainDone(). because the drainManager variable is not used properly and does not appear to be necessary it has been removed with this patch.
2013-01-28merged 798c2cec8e37 and e96ff45795bcNilay Vaish
2013-01-28stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3Andreas Hansson
This patch bumps the stats for 20.parser for ARM o3-timing to reflect a namechange of the branch predictor.
2013-01-28ruby: remove get_time()Nilay Vaish
This patch replaces get_time() in *.sm files with curCycle() which is now possible since controllers are clocked objects.
2013-01-28ruby: remove call to curCycle in panic()Nilay Vaish
The panic() function already prints the current tick value. This call to curCycle() is as such redundant. Since we are trying to move towards multiple clock domains, this call will print misleading time.
2013-01-24regressions: update stats due to branch predictor changesNilay Vaish
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. --HG-- rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
2013-01-22o3 cpu: fix zero reg problemAndrea Pellegrini
There was an issue w/ the rename logic, which would assign a previous physical register to the ZeroReg architectural register in x86. This issue was giving problems for instructions squashed in threads w/ ID different from 0, sometimes allowing non-mispredicted instructions to obtain a value different from zero when reading the zeroReg.
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
The changes made by the changeset 270c9a75e91f do not work well with switching of cpus. The problem is that decoder for the old thread context holds state that is not taken over by the new decoder. This patch adds a takeOverFrom() function to Decoder class in each ISA. Except for x86, functions in other ISAs are blank. For x86, the function copies state from the old decoder to the new decoder.
2013-01-21scons: Disable protobuf if pkg-config and CheckLib failsAndreas Hansson
This patch changes the use of pkg-config such that protobuf is still evaluated with CheckLib even if it fails. This is to allow setups where libprotobuf is available, but not configured through protobuf. Moreover, if CheckLib fails to use libprotobuf then all the tracing is disabled, but scons is allowed to continue with a warning.
2013-01-19O3 IEW: Make incrWb and decrWb clearerJoel Hestness
Move the increment/decrement of wbOutstanding outside of the comparison in incrWb and decrWb in the IEW. This also fixes a compiler bug with gcc 4.4.7, which incorrectly optimizes "-- ==" as "-=".
2013-01-17ruby: remove calls to g_system_ptr->getTime()Nilay Vaish
This patch further removes calls to g_system_ptr->getTime() where ever other clocked objects are available for providing current time.
2013-01-15x86 regressions: updates due to new instructions and cpuidNilay Vaish
2013-01-15x86 cpuid: enable clflushNilay Vaish
Note that clflush is only being enabled. It is not implemented in actual. A warning is printed if the cpu encounters a clflush instruction. We need to enable this instruction in cpuid since JRE 1.7 tests for it.
2013-01-15x86: implements fsin, fcos instructionsNilay Vaish
2013-01-15x86: implements emms instructionNilay Vaish
2013-01-15x86: implement fabs, fchs instructionsNilay Vaish
2013-01-14regressions: update stats due to changes in ruby obj hierarchyNilay Vaish
2013-01-14config: move ruby objects under ruby_system in obj hierarchyMalek Musleh
This patch moves the contollers to be children of the ruby_system instead of 'system' under the python object hierarchy. This is so that these objects can inherit some of the ruby_system's parameter values without resorting to calling a global system pointer during run-time. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-14ruby sequencer: converts cycles to ticks in deadlock panic()Malek Musleh
This patch converts the panic() print outs in the Sequencer::wakeup() call from ruby cycles to Ticks(). This makes it easier to debug deadlocks with the ProtocolTrace flag so the issue time indicated in the panic message can be quickly searched for. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-01-14Ruby: remove reference to g_system_ptr from class MessageNilay Vaish
This patch was initiated so as to remove reference to g_system_ptr, the pointer to Ruby System that is used for getting the current time. That simple change actual requires changing a lot many things in slicc and garnet. All these changes are related to how time is handled. In most of the places, g_system_ptr has been replaced by another clock object. The changes have been done under the assumption that all the components in the memory system are on the same clock frequency, but the actual clocks might be distributed.
2013-01-14Ruby: use ClockedObject in Consumer classNilay Vaish
Many Ruby structures inherit from the Consumer, which is used for scheduling events. The Consumer used to relay on an Event Manager for scheduling events and on g_system_ptr for time. With this patch, the Consumer will now use a ClockedObject to schedule events and to query for current time. This resulted in several structures being converted from SimObjects to ClockedObjects. Also, the MessageBuffer class now requires a pointer to a ClockedObject so as to query for time.
2013-01-14scons: Address clang 3.2 compilation errorAndreas Hansson
This patch fixes a compilation error encountered using clang 3.2 on OSX.
2013-01-14stats: Bump failing x86 regression statsAndreas Hansson
This patch bumps the stats of mcf and twolf for the o3 CPU such that the regressions pass.
2013-01-12base simple cpu: removes commented out code about cache opsNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08stats: update stats for previous six changesAli Saidi
2013-01-08util: add writefile to m5 util program for x86Lluís Vilanova
2013-01-08util: add m5_fail op.Lluís Vilanova
Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully. For example, one can use: /path/to/benchmark args || /sbin/m5 fail 1 and thus ensure gem5 will exit with an error if the benchmark fails.
2013-01-08sim: Fix early termination in multi-core simulation under SE mode.Tao Zhang
When "-I" (maximum instruction number) and "-F" (fastforward instruction number) are applied together, gem5 immediately exits after the cpu switching. The reason is that multiple exit events may be generated in the same cycle by Atomic CPU and inserted to mainEventQueue. However, mainEventQueue can only serve one exit event in one cycle. Therefore, the rest exit events are left in mainEventQueue without being descheduled or deleted, which causes gem5 exits immediately after the system resumes by cpu switching.
2013-01-08arm: add access syscall for ARM SE modeMitch Hayenga
This patch adds the "access" syscall for ARM SE as required by some spec2006 benchmarks.
2013-01-08mem: Make LL/SC locks fine grainedMitch Hayenga
The current implementation in gem5 just keeps a list of locks per cacheline. Due to this, a store to a non-overlapping portion of the cacheline can cause an LL/SC pair to fail. This patch simply adds an address range to the lock structure, so that the lock is only invalidated if the store overlaps the lock range.
2013-01-08mem: Fix use-after-free bugMitch Hayenga
Running with valgrind I noticed a use after free originating from simple_mem.cc. It looks like this is a known issue and this additional call site was missed in an earlier patch.
2013-01-07dev: Fix infinite recursion in DMA devicesAndreas Sandberg
The DMA device sometimes calls the process() method on a completion event directly instead of scheduling it on the current tick. This breaks some devices that assume that the completion handler won't be called until the current event handler has returned. Specifically, it causes infinite recursion in the IdeDisk component because it does not advance its chunk generator until after a dmaRead()/dmaWrite() has returned. This changeset removes this mico-optimization and schedules the event in the current tick instead. This way the semantics event handling stay the same even when the delay is 0.
2013-01-07util: Fix stack corruption in the m5 utilAndreas Sandberg
The number of arguments specified when calling parse_int_args() in do_exit() is incorrect. This leads to stack corruption since it causes writes past the end of the ints array.
2013-01-07stats: Fix swig wrapping for Tick in statsSascha Bischoff
Tick was not correctly wrapped for the stats system, and therefore it was not possible to configure the stats dumping from the python scripts without defining Ticks as long long. This patch fixes the wrapping of Tick by copying the typemap of uint64_t to Tick.
2013-01-07stats: update stats for previous changes.Ali Saidi
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
Cleanup the serialization code for the simple CPUs and the O3 CPU. The CPU-specific code has been replaced with a (un)serializeThread that serializes the thread state / context of a specific thread. Assuming that the thread state class uses the CPU-specific thread state uses the base thread state serialization code, this allows us to restore a checkpoint with any of the CPU models.
2013-01-07tests: Add CPU switching testsAndreas Sandberg
This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.