gem5 - gem5

Age	Commit message (Expand)	Author
2018-11-20	sim: Deschedule existing events when destructing an event queue.	Gabe Black
2018-11-19	base: Don't let exceptions leak from the to_number utility function.	Gabe Black
2018-11-19	systemc: Stop explicitly adding the systemc ext dir to CPPPATH.	Gabe Black
2018-11-19	systemc: Put systemc headers in the include path when supported.	Gabe Black
2018-11-19	systemc: Increase the stack size for the sc_main fiber to 8MB.	Gabe Black
2018-11-18	base: Set up a guard page for fiber stacks.	Gabe Black
2018-11-18	mem-cache: a missing cast was truncating addresses	Javier Bueno
2018-11-17	cpu: Fix LTAGE max number of allocations on update	Pau Cabre
2018-11-17	configs: Added an option for choosing branch predictor type	Pau Cabre
2018-11-16	sim: Fix data type of ticks per second before passing it to C++	Srikant Bharadwaj
2018-11-16	mem: avoid calling regStat twice on a QoSPolicy	Matteo Andreozzi
2018-11-16	cpu: Fix the usage of const DynInstPtr	Rekai Gonzalez-Alberquilla
2018-11-15	mem-cache: fix invalid iterator access	Javier Bueno
2018-11-15	mem-cache: Make StridePrefetcher use Replacement Policies	Daniel
2018-11-15	mem-cache: Add invalidation function to StrideEntry	Daniel
2018-11-15	mem-cache: Make PCTable context independent	Daniel
2018-11-15	mem-cache: Vectorize StridePrefetcher's entries.	Daniel
2018-11-15	mem-cache: Return entry in StridePrefetcher::pcTableHit()	Daniel
2018-11-15	mem-cache: Cleanup prefetchers	Daniel
2018-11-15	scons: add --gold-linker to link with the gold linker	Ciro Santilli
2018-11-14	cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal	Pau Cabre
2018-11-14	mem-cache: Remove Cache dependency from Tags	Daniel R. Carvalho
2018-11-14	mem-cache: Move access latency calculation to Cache	Daniel R. Carvalho
2018-11-14	arch-arm: Print register name when warning on AT instructions	Giacomo Travaglini
2018-11-14	mem-cache: implement a probe-based interface	Javier Bueno
2018-11-14	sim: Move BitUnion overloading to show/parseParams	Giacomo Travaglini
2018-11-14	sim: Move paramIn/Out definition to header file	Giacomo Travaglini
2018-11-13	cpu: Fixed PC shifting on LTAGE branch predictor	Pau Cabre
2018-11-13	mem-cache: Align how we handle requests in atomic with timing	Nikos Nikoleris
2018-11-12	systemc: Push python headers on top of sources	Giacomo Travaglini
2018-11-12	systemc: Stop using python to set/manage the global time resolution.	Gabe Black
2018-11-12	sim: Push the global frequency management code into C++.	Gabe Black
2018-11-09	configs: Revamp ruby mem test to align with MemTest	Nikos Nikoleris
2018-11-09	systemc: Get rid of a duplicated base class initializer for sc_fifo.	Gabe Black
2018-11-09	systemc: Add a missing "const" on one of the sc_event operators.	Gabe Black
2018-11-09	systemc: Only build python utility code if python is enabled.	Gabe Black
2018-11-09	systemc: Separate and conditionalize exposing sc_main to python.	Gabe Black
2018-11-09	systemc: Seperate out the sc_main fiber and its bookkeeping.	Gabe Black
2018-11-09	systemc: Stop using python init to set up predefined message ids.	Gabe Black
2018-11-09	systemc: Wrap some report maps in functions.	Gabe Black
2018-11-08	configs: Add missing path to ruby imports	Daniel R. Carvalho
2018-11-07	mem-ruby: Use Packet writing functions instead of memcpy	Daniel R. Carvalho
2018-11-07	misc: Update workflow requirements in CONTRIBUTING.md	Tony Gutierrez
2018-11-07	arch-arm: Deprecate usage of legacy bootloader patching	Giacomo Travaglini
2018-11-07	arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32	Giacomo Travaglini
2018-11-07	arch-arm: Implement AArch32 RVBAR	Giacomo Travaglini
2018-11-07	arch-arm: Remove SCTLR.VE bit	Giacomo Travaglini
2018-11-07	arch-arm: Refactor ISA::clear by adding a ISA::clear32 method	Giacomo Travaglini
2018-11-07	arch-arm: Remove MISCREG commented numbers	Giacomo Travaglini
2018-11-07	systemc: Fix some paths in the tlm SCons(script\|struct).	Gabe Black