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2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
The phrase is no longer valid since we do not distinguish between inter and intra chip communication.
2014-04-03sim: Add the ability to lock and migrate between event queuesAndreas Sandberg
We need the ability to lock event queues to enable device accesses across threads. The serviceOne() method now takes a service lock prior to handling a new event. By locking an event queue, a different thread/eq can effectively execute in the context of the locked event queue. To simplify temporary event queue migrations, this changeset introduces the EventQueue::ScopedMigration class that unlocks the current event queue, locks a new event queue, and updates the current event queue variable. In order to prevent deadlocks, event queues need to be released when waiting on barriers. This is implemented using the EventQueue::ScopedRelease class. An instance of this class is, for example, used in the BaseGlobalEvent class to release the event queue when waiting on the synchronization barrier. The intended use for this functionality is when devices need to be accessed across thread boundaries. For example, when fast-forwarding, it might be useful to run devices and CPUs in separate threads. In such a case, the CPU locks the device queue whenever it needs to perform IO. This functionality is primarily intended for KVM. Note: Migrating between event queues can lead to non-deterministic timing. Use with extreme care! --HG-- extra : rebase_source : 23e3a741a1fd73861d1339782dbbe1bc76285315
2014-04-01ext: add McPAT sourceAnthony Gutierrez
this patch adds the source for mcpat, a power, area, and timing modeling framework.
2014-04-01arm: fix typos in makefile for ARM m5 util and link staticallyAnthony Gutierrez
1) fixes a typo for clean target libgemOpJni.so -> libgem5OpJni.so 2) addes jni_gem5Op.h to clean since it is added during make 3) links the m5 utility statically since it won't work on some images otherwise
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
A recent changeset altered the default memory class to DRAMCtrl. In se mode, ruby uses the physical memory to check if a given address is within the bounds of the physical memory. SimpleMemory is enough for this. Moreover, SimpleMemory does not check whether it is connected or not, something which DRAMCtrl does.
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
This patch fixes violation of TSO in the O3CPU, as all loads must be ordered with all other loads. In the LQ, if a snoop is observed, all subsequent loads need to be squashed if the system is TSO. Prior to this patch, the following case could be violated: P0 | P1 ; MOV [x],mail=/usr/spool/mail/nilay | MOV EAX,[y] ; MOV [y],mail=/usr/spool/mail/nilay | MOV EBX,[x] ; exists (1:EAX=1 /\ 1:EBX=0) [is a violation] The problem was found using litmus [http://diy.inria.fr]. Committed by: Nilay Vaish <nilay@cs.wisc.edu
2014-03-23stats: Update stats for DRAM changesAndreas Hansson
This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
This patch adds stats for tracking the number of reads/writes per bus turn around, and also adds hysteresis to the write-to-read switching to ensure that the queue does not oscilate around the low threshold.
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
Make the default memory type DDR3-1600 x64, and use the open-adaptive page policy. This change is aiming to ensure that users by default are using a realistic memory system.
2014-03-23mem: Add close adaptive paging policy to DRAM controller modelWendy Elsasser
This patch adds a second adaptive page policy to the DRAM controller, closing the page unless there are already queued accesses to the open page.
2014-03-23mem: DRAM controller tidying upAndreas Hansson
Minor tidying up and removing of redundant code, including the printing of queue state every million accesses.
2014-03-23mem: Fix bug in DRAM bytes per activateAndreas Hansson
This patch ensures that we do not sample the bytes per activate when the row has already been closed.
2014-03-23mem: Limit the accesses to a page before forcing a prechargeAndreas Hansson
This patch adds a basic starvation-prevention mechanism where a DRAM page is forced to close after a certain number of accesses. The limit is combined with the open and open-adaptive page policy and if reached causes an auto-precharge.
2014-03-23mem: Make DRAM write queue draining more aggressiveAndreas Hansson
This patch changes the triggering condition for the write draining such that we grab the opportunity to issue writes if there are no reads waiting (as opposed to waiting for the writes to reach the high threshold). As a result, we potentially drain some of the writes in read idle periods (if any). A low threshold is added to be able to control how many write bursts are kept in the memory controller queue (acting as on-chip storage). The high and low thresholds are updated to sensible values for a 32/64 size write buffer. Note that the thresholds should be adjusted along with the queue sizes. This patch also adds some basic initialisation sanity checks and moves part of the initialisation to the constructor.
2014-03-23config: Add a DRAM efficiency-sweep scriptAndreas Hansson
This patch adds a configuration that simplifies evaluation of DRAM controller configurations by automating a sweep of stride size and bank parallelism. It works in a rather unconventional way, as it needs to print the traffic generator stimuli based on the memory organisation. Hence, it starts by configuring the memory, then it prints a traffic-generator config file, and loads it. The resulting stats have one period per data point, identified by the stride size, and the number of banks being used.
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
This patch enables a new 'DRAM' mode to the existing traffic generator, catered to generate specific requests to DRAM based on required hit length (stride size) and bank utilization. It is an add on to the Random mode. The basic idea is to control how many successive packets target the same page, and how many banks are being used in parallel. This gives a two-dimensional space that stresses different aspects of the DRAM timing. The configuration file needed to use this patch has to be changed as follow: (reference to Random Mode, LPDDR3 memory type) 'STATE 0 10000000000 RANDOM 50 0 134217728 64 3004 5002 0' -> 'STATE 0 10000000000 DRAM 50 0 134217728 32 3004 5002 0 96 1024 8 6 1' The last 4 parameters to be added are: <stride size (bytes), page size(bytes), number of banks available in DRAM, number of banks to be utilized, address mapping scheme> The address mapping information is used to get the stride address stream of the specified size and to know where to find the bank bits. The configuration file has a parameter where '0'-> RoCoRaBaCh, '1'-> RoRaBaCoCh/RoRaBaChCo address-mapping schemes. Note that the generator currently assumes a single channel and a single rank. This is to avoid overwhelming the traffic generator with information about the memory organisation.
2014-03-23mem: DDR3 config for comparing with DRAMSim2Neha Agarwal
This patch adds a new DDR3 configuration to match with the parameters that are specified in one of the DDR3 configs used in DRAMSim2.
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
This patch adds the row bits to the name of the address mapping schemes to make it more clear that all the current schemes places the row bits as the most significant bits.
2014-03-23scons: Shush sconsCurtis Dunham
make 'scons -s' actually silent.
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
Check the right flag.
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson
This patch moves the Ruby-related debug flags to the ruby sub-directory, and also removes the state SConsopts that add the no-longer-used NO_VECTOR_BOUNDS_CHECK.
2014-03-23util: Add support for detection of gzipped packet tracesAndreas Hansson
This patch adds support for automatically detecting a gzipped packet trace, thus accepting either a compressed or uncompressed trace.
2014-03-23mem: Include the DRAMSim2 wrapper in NULL buildAndreas Hansson
This patch makes sure DRAMSim2 is included in a build of the NULL ISA.
2014-03-23ext: Fix typo in DRAMSim2 SConscriptAndreas Hansson
This patch fixes a typo in the SConscript which caused the DRAMSim2 sources to be built without the appropriate flags.
2014-03-23mem: CommMonitor trace warn on non-timing modeSascha Bischoff
Add a warning to the CommMonitor which will alert the user if they try and record a trace when the system is not in timing mode.
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
Prevent incomplete configuration of TrafficGen class from causing segmentation faults. If an 'INIT' line is not present in the configuration file then the currState variable will remain uninitialized which may result in a crash.
2014-03-23dev: Fix IsaFake's cxx_header settingAndrew Bardsley
cxx_header was set incorrectly on IsaFake
2014-03-23arm: m5ops readfile64 args broken, offset coming through garbageEric Van Hensbergen
There were several sections of the m5ops code which were essentially copy/pasted versions of the 32-bit code. The problem is that some of these didn't account fo4 64-bit registers leading to arguments being in the wrong registers. This patch addresses the args for readfile64, writefile64, and addsymbol64 -- all of which seemed to suffer from a similar set of problems when moving to 64-bit.
2014-03-23base: Fix error message time unit (cycle -> tick)Andreas Hansson
This patch fixes the unit used in all error messages.
2014-03-20stats: updates due to changes to ruby config scriptsNilay Vaish
These updates to ruby regression stats are due to renaming piobus to iobus and dropping piobus in the se mode.
2014-03-20ruby: consumer: avoid accessing wakeup times when waking upNilay Vaish
Each consumer object maintains a set of tick values when the object is supposed to wakeup and do some processing. As of now, the object accesses this set both when scheduling a wakeup event and when the object actually wakes up. The set is accessed during wakeup to remove the current tick value from the set. This functionality is now being moved to the scheduling function where ticks are removed at a later time.
2014-03-20ruby: garnet: convert network interfaces into clocked objectsNilay Vaish
This helps in configuring the network interfaces from the python script and these objects no longer rely on the network object for the timing information.
2014-03-20ruby: slicc: code refactorNilay Vaish
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish
2014-03-20config: fs.py: move creating of test/drive systems to functionsNilay Vaish
The code that creates test and drive systems is being moved to separate functions so as to make the code more readable. Ultimately the two functions would be combined so that the replicated code is eliminated.
2014-03-20config: remove ruby_fs.pyNilay Vaish
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
2014-03-20ruby: no piobus in se modeNilay Vaish
Piobus was recently added to se scripts for ruby so that the interrupt controller can be connected to something (required since the interrupt controller sends address range messages). This patch removes the piobus and instead, the pio port of ruby port will now ignore the range change messages in se mode.
2014-03-17config: ruby: remove piobus from protocolsNilay Vaish
This patch removes the piobus from the protocol config files. The ports are now connected to the piobus in the Ruby.py file.
2014-03-17ruby: remove some of the unnecessary codeNilay Vaish
2014-03-16kvm: Clean up signal handlingAndreas Sandberg
KVM used to use two signals, one for instruction count exits and one for timer exits. There is really no need to distinguish between the two since they only trigger exits from KVM. This changeset unifies and renames the signals and adds a method, kick(), that can be used to raise the control signal in the vCPU thread. It also removes the early timer warning since we do not normally see if the signal was delivered. --HG-- extra : rebase_source : cd0e45ca90894c3d6f6aa115b9b06a1d8f0fda4d
2014-03-16kvm: x86: Adjust PC to remove the CS segment base addressAndreas Sandberg
gem5 seems to store the PC as RIP+CS_BASE. This is not what KVM expects, so we need to subtract CS_BASE prior to transferring the PC into KVM. This changeset adds the necessary PC manipulation and refactors thread context updates slightly to avoid reading registers multiple times from KVM. --HG-- extra : rebase_source : 3f0569dca06a1fcd8694925f75c8918d954ada44
2014-03-16kvm: x86: Add support for x86 INIT and STARTUP handlingAndreas Sandberg
This changeset adds support for INIT and STARTUP IPI handling. We currently handle both of these interrupts in gem5 and transfer the state to KVM. Since we do not have a BIOS loaded, we pretend that the INIT interrupt suspends the CPU after reset. --HG-- extra : rebase_source : 7f3b25f3801d68f668b6cd91eaf50d6f48ee2a6a
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
This patch merely tidies up the CPU and ThreadContext getters by making them const where appropriate.
2014-03-07arm: Handle functional TLB walks properlyGeoffrey Blake
The table walker code currently accounts for two types of walks, Atomic and Timing, and treats them differently. Atomic walks keep a single instance of WalkerState around for all walks to use in currState. Timing mode keeps a queue of in-flight WalkerStates and maintains currState as NULL between walks. If a functional walk is done during Timing mode, it is treated as an atomic walk and either creates a persistent WalkerState if in between Timing walks, or stomps an existing currState for an in-progress Timing walk. This patch distinguishes functional walks as being able to exist at any time and sets up a temporary WalkerState for its exclusive use and then cleans up when finished, leaving any in progress Atomic or Timing walks undisturbed.
2014-03-07mem: Fix incorrect assert failure in the CachePrakash Ramrakhyani
This patch fixes an assert condition that is not true at all times. There are valid situations that arise in dual-core dual-workload runs where the assert condition is false. The function call following the assert however needs to be called only when the condition is true (a block cannot be invalidated in the tags structure if has not been allocated in the structure, and the tempBlock is never allocated). Hence the 'assert' has been replaced with an 'if'.
2014-03-07mem: Edit proto Packet and enhance the python scriptRadhika Jagtap
This patch changes the decode script to output the optional fields of the proto message Packet, namely id and flags. The flags field is set by the communication monitor. The id field is useful for CPU trace experiments, e.g. linking the fetch side to decode side. It had to be renamed because it clashes with a built in python function id() for getting the "identity" of an object. This patch also takes a few common function definitions out from the multiple scripts and adds them to a protolib python module.
2014-03-07scons: Fix clang version identification for OSXMitch Hayenga
The version string may have additional trailing information
2014-03-07misc: Add panic_if / fatal_if / chatty_assertStephan Diestelhorst
This snippet can be used to replace if + {panics, fatals, asserts} constructs. The idea is to have both the condition checking and a verbose printout in a single statement. The interface is as follows: panic_if(foo != bar, "These should be equal: foo %i bar %i", foo, bar); fatal_if(foo != bar, "These should be equal: foo %i bar %i", foo, bar); chatty_assert(foo == bar, "These should be equal: foo %i bar %i", foo, bar);