gem5 - gem5

Age	Commit message (Collapse)	Author
2010-11-26	IGbE: return 0 on an invalid descriptor size instead of -1.	Ali Saidi
	Asserts where descSize() get called with assert if we end up returning 0.
2010-11-23	Copyright: Add AMD copyright to the param changes I just made.	Gabe Black

2010-11-23	Params: Add parameter types for IP addresses in various forms.	Gabe Black
	New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately.
2010-11-23	X86: Loosen an assert for x86 and connect the APIC ports when caches are used.	Gabe Black

2010-11-23	X86: Obey the PCD (cache disable) bit in the page tables.	Gabe Black

2010-11-22	X86: Mark IO space accesses as uncachable.	Gabe Black

2010-11-22	X86: Remove reserved* from the m5 utility program for x86.	Gabe Black

2010-11-22	IDE,X86: Fix IDE controller BAR configuration for x86.	Gabe Black

2010-11-20	random: small comment about our random number generator and its origin	Nathan Binkert

2010-11-19	SE: Fix simulating more than 4GB of RAM in SE mode	Ali Saidi
	This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style.
2010-11-19	SCons: Fix compilation on OS X	Ali Saidi

2010-11-19	SCons: Support building without an ISA	Ali Saidi

2010-11-18	O3: Fix fp destination register flattening, and index offset adjusting.	Gabe Black
	This change makes O3 flatten floating point destination registers, and also fixes misc register flattening so that it's correctly repositioned relative to the resized regions for integer and floating point indices. It also fixes some overly long lines.
2010-11-17	Config: Change misleading "cycle" message to say "tick".	Gabe Black
	Most of the messages in the config scripts that report a time value already print "@ tick" followed by the current tick value, but a few were printing "@ cycle". Since this is a distinction that's frequently confusing to new users, this changes those message to the more accurate and consistent "@ tick".
2010-11-15	Stats: Update the O3 fetch stats for SPARC.	Gabe Black

2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black

2010-11-15	O3: reset architetural state by calling clear()	Ali Saidi

2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi

2010-11-15	Regressions: Update regressions for SIMD opclass changes	Ali Saidi

2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli

2010-11-15	ARM: Compile O3 CPU by default	Ali Saidi

2010-11-15	O3: prevent a squash when completeAcc() modifies misc reg through TC.	Min Kyu Jeong
	This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods
2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵	Ali Saidi
	accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation.
2010-11-15	SCons: Cleanup SCons output during compile	Ali Saidi

2010-11-15	ARM: Update regressions for CLCD and KMI additions	Ali Saidi

2010-11-15	ARM: Add a Keyboard Mouse Interface controller	William Wang

2010-11-15	ARM: Implement a CLCD Frame buffer	William Wang

2010-11-15	ARM: Add support for GDB on ARM	William Wang
	--HG-- rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
2010-11-15	ARM: Make utility.hh meet style guidelines	Ali Saidi

2010-11-15	ARM: Add support for a dumb IDE controller	Ali Saidi

2010-11-15	ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.	Ali Saidi

2010-11-15	ARM: Add support for switching CPUs	Ali Saidi

2010-11-15	ARM: Use the correct delete operator for RFE	Ali Saidi

2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
	Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect.
2010-11-15	CPU: Fix bug when a split transaction is issued to a faster cache	Ali Saidi
	In the case of a split transaction and a cache that is faster than a CPU we could get two responses before next_tick expires. Add an event that is scheduled in this case and return false rather than asserting.
2010-11-15	ARM: Do something predictable for an UNPREDICTABLE branch.	Ali Saidi

2010-11-11	Params: Fix an off by one error and a misleading comment.	Gabe Black

2010-11-11	SimObject: Add a comment near clear_child that it's unlikely to be called.	Gabe Black

2010-11-11	SPARC: Clean up some historical style issues.	Gabe Black

2010-11-10	Update EIO regressions for last set of patches	Ali Saidi

2010-11-09	scons: Work around for old versions of scons mistaking strings for sequences.	Gabe Black

2010-11-09	SimObject: Use "self" when calling the clear_child method.	Gabe Black

2010-11-08	X86: Fix X86_FS compilation.	Gabe Black

2010-11-08	ARM: Update SE stats for TLB stats additions	Ali Saidi

2010-11-08	ARM: Add full-system regressions	Ali Saidi

2010-11-08	ARM: Add some TLB statistics for ARM	Ali Saidi

2010-11-08	ARM: Add checkpointing support	Ali Saidi

2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi

2010-11-08	ARM: Keep the warnings to a minimum.	Ali Saidi
	These warnings still need to be addresses, but pages of them is counterproductive.
2010-11-08	Mem: Finish half-baked support for mmaping file in physmem.	Ali Saidi
	Physmem has a parameter to be able to mem map a file, however it isn't actually used. This changeset utilizes the parameter so a file can be mmapped.