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AgeCommit message (Collapse)Author
2011-02-18inorder: update graduation unitKorey Sewell
make sure instructions are able to commit before writing back to the RF do not commit more than 1 non-speculative instruction per cycle
2011-02-18inorder: recognize isSerializeAfter flagKorey Sewell
keep track of when an instruction needs the execution behind it to be serialized. Without this, in SE Mode instructions can execute behind a system call exit().
2011-02-18inorder: update default thread size(=1)Korey Sewell
a lot of structures get allocated based off that MaxThreads parameter so this is an effort to not abuse it
2011-02-18inorder: don't overuse getLatency()Korey Sewell
resources don't need to call getLatency because the latency is already a member in the class. If there is some type of special case where different instructions impose a different latency inside a resource then we can revisit this and add getLatency() back in
2011-02-18inorder: update max. resource bandwidthsKorey Sewell
each resource has a certain # of requests it can take per cycle. update the #s here to be more realistic based off of the pipeline width and if the resource needs to be accessed on multiple cycles
2011-02-18inorder: cleanup in destructorsKorey Sewell
cleanup hanging pointers and other cruft in the destructors
2011-02-18inorder: fix cache/fetch unit memory leaksKorey Sewell
--- need to delete the cache request's data on clearRequest() now that we are recycling requests --- fetch unit needs to deallocate the fetch buffer blocks when they are replaced or squashed.
2011-02-18inorder: remove events for zero-cycle resourcesKorey Sewell
if a resource has a zero cycle latency (e.g. RegFile write), then dont allocate an event for it to use
2011-02-18inorder: update pipeline interface for handling finished resource reqsKorey Sewell
formerly, to free up bandwidth in a resource, we could just change the pointer in that resource but at the same time the pipeline stages had visibility to see what happened to a resource request. Now that we are recycling these requests (to avoid too much dynamic allocation), we can't throw away the request too early or the pipeline stage gets bad information. Instead, mark when a request is done with the resource all together and then let the pipeline stage call back to the resource that it's time to free up the bandwidth for more instructions *** inteface notes *** - When an instruction completes and is done in a resource for that cycle, call done() - When an instruction fails and is done with a resource for that cycle, call done(false) - When an instruction completes, but isnt finished with a resource, call completed() - When an instruction fails, but isnt finished with a resource, call completed(false) * * * inorder: tlbmiss wakeup bug fix
2011-02-18inorder: remove request map, use request vectorKorey Sewell
take away all instances of reqMap in the code and make all references use the built-in request vectors inside of each resource. The request map was dynamically allocating a request per instruction. The request vector just allocates N number of requests during instantiation and then the surrounding code is fixed up to reuse those N requests *** setRequest() and clearRequest() are the new accessors needed to define a new request in a resource
2011-02-18inorder: add valid bit for resource requestsKorey Sewell
this will allow us to reuse resource requests within a resource instead of always dynamically allocating
2011-02-18inorder: remove reqRemoveListKorey Sewell
we are going to be getting away from creating new resource requests for every instruction so no more need to keep track of a reqRemoveList and clean it up every tick
2011-02-18inorder: initialize res. req. vectors based on resource bandwidthKorey Sewell
first change in an optimization that will stop InOrder from allocating new memory for every instruction's request to a resource. This gets expensive since every instruction needs to access ~10 requests before graduation. Instead, the plan is to allocate just enough resource request objects to satisfy each resource's bandwidth (e.g. the execution unit would need to allocate 3 resource request objects for a 1-issue pipeline since on any given cycle it could have 2 read requests and 1 write request) and then let the instructions contend and reuse those allocated requests. The end result is a smaller memory footprint for the InOrder model and increased simulation performance
2011-02-12inorder:regress: host-inst-rate improved ~58%Korey Sewell
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-12inorder: clean up the old way of inst. schedulingKorey Sewell
remove remnants of old way of instruction scheduling which dynamically allocated a new resource schedule for every instruction
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
allow the pipeline and resources to use the cached instruction schedule and resource sked iterator
2011-02-12inorder: define iterator for resource schedulesKorey Sewell
resource skeds are divided into two parts: front end (all insts) and back end (inst. specific) each of those are implemented as separate lists, so this iterator wraps around the traditional list iterator so that an instruction can walk it's schedule but seamlessly transfer from front end to back end when necessary
2011-02-12inorder: stage scheduler for front/back end schedule creationKorey Sewell
add a stage scheduler class to replace InstStage in pipeline_traits.cc use that class to define a default front-end, resource schedule that all instructions will follow. This will also replace the back end schedule in pipeline_traits.cc. The reason for adding this is so that we can cache instruction schedules in the future instead of calling the same function over/over again as well as constantly dynamically alllocating memory on every instruction to try to figure out it's schedule
2011-02-12inorder: cache instruction schedulesKorey Sewell
first step in a optimization to not dynamically allocate an instruction schedule for every instruction but rather used cached schedules
2011-02-12inorder: comments for resource sked classKorey Sewell
2011-02-12inorder: remove unused fileKorey Sewell
inst_buffer file isn't used , so remove it
2011-02-12inorder: remove unused isa opsKorey Sewell
pass/fail ops were used for testing but arent part of isa
2011-02-11Stats: Update the statistics for vnc patch.Ali Saidi
2011-02-11VNC/ARM: Use VNC server and add support to boot into X11Ali Saidi
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-11Serialization: Allow serialization of stl listsAli Saidi
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
When a table walk is initiated by the fetch stage, the CPU can potentially move to the idle state and never wake up. The fetch stage must call cpu->wakeCPU() when a translation completes (in finishTranslation()).
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
Uncacheable requests were set as such only in atomic mode. currState->delayed is checked in place of currState->timing for resetting currState in atomic mode.
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk ↵Ali Saidi
occurs. This change fixes an issue where a DTLB fault occurs and redirects fetch to handle the fault and the ITLB requires a walk which delays translation. In this case the status of the cpu isn't updated appropriately, and an additional instruction fetch occurs. Eventually this hits an assert as multiple instruction fetches are occuring in the system and when the second one returns the processor is in the wrong state. Some asserts below are removed because it was always true (typo) and the state after the initiateAcc() the processor could be in any valid state when a d-side fault occurs.
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-11ARM: Fix timer calculations.Ali Saidi
The timer calculations were a bit off so time would run faster than it otherwise should
2011-02-11Timesync: Make sure timesync event is setup after curTick is unserializedAli Saidi
Setup initial timesync event in initState or loadState so that curTick has been updated to the new value, otherwise the event is scheduled in the past.
2011-02-09Ext: Add X11 keysym header files to ext directory.Ali Saidi
2011-02-09ruby: removed duplicate make response callBrad Beckmann
2011-02-08regess: protocol regression tester updatesBrad Beckmann
2011-02-08memtest: due to contention increase, increased deadlock thresholdBrad Beckmann
2011-02-08config: fixed minor bug connecting dma devices to rubyBrad Beckmann
2011-02-08MESI CMP: Unset TBE pointer in L2 cache controllerNilay Vaish
The TBE pointer in the MESI CMP implementation was not being set to NULL when the TBE is deallocated. This resulted in segmentation fault on testing the protocol when the ProtocolTrace was switched on.
2011-02-07Stats: Re update stats.Gabe Black
2011-02-07Stats: Back out broken update.Gabe Black
2011-02-07X86: Obey the wp bit of CR0.Tim Harris
If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode.
2011-02-07X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.Tim Harris
During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address)
2011-02-07X86: Fix JMP_FAR_I to unpack a far pointer correctly.Tim Harris
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like it should, and also putting the components in the wrong registers for use by other microcode.
2011-02-07X86: Read the LDT/GDT at CPL0 when executing an iret.Tim Harris
During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated).
2011-02-07Orion: Replace printf() with fatal()Nilay Vaish
The code for Orion 2.0 makes use of printf() at several places where there as an error in configuration of the model. These have been replaced with fatal().
2011-02-07ruby: add stdio header in SRAM.hhKorey Sewell
missing header file caused RUBY_FS to not compile
2011-02-07X86: Add stats for the new x86 fs regressions.Gabe Black
2011-02-07X86: Add scripts to support X86 FS configurations in the regressions.Gabe Black
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
2011-02-07X86: Fix compiling vtophys.ccGabe Black