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2015-11-27base: Add support for changing output directoriesAndreas Sandberg
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++. This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-02-29util: update Java JNI interface to m5opsPrakash Ramrakhyani
Synchronize with ab19693da "pseudo inst,util: Add optional key to initparam pseudo instruction"
2015-08-10mem, cpu: Add assertions to snoop invalidation logicStephan Diestelhorst
This patch adds assertions that enforce that only invalidating snoops will ever reach into the logic that tracks in-order load completion and also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds some comments to MSHR::replaceUpgrades().
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
Writes to locked memory addresses (LLSC) did not wake up the locking CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU, recvAtomicSnoop was checking if the incoming packet was an invalidation (isInvalidate) and only then handled a locked snoop. But, writes are seen instead of invalidates when running without caches (fast-forward configurations). As as simple fix, now handleLockedSnoop is also called even if the incoming snoop packet are from writes.
2016-02-29arm: Squash after returning from exceptions in v7Mitch Hayenga
Properly done for the ERET instruction in v8, but not for v7. Many control register changes are only visible after explicit instruction synchronization barriers or exception entry/exit. This means mode changing instructions should squash any younger in-flight speculative instructions.
2016-02-29base: support gzip-compressed object filesCurtis Dunham
2016-02-24stats: Update stats to reflect forwarding of InvalidateReqAndreas Hansson
2016-02-24mem: Ensure that InvalidateReq is not forwarded as ReadExReqAndreas Hansson
This patch fixes an issue where an InvalidationReq only traversed one level of the cache hierarchy, and was subsequently turned into a ReadExReq due to it needing writable, and the command not being checked for explicitly.
2016-02-24cpu: TraceGen fix for tick frequency checkMatteo Andreozzi
Bug fix for check on protobuf file frequency being different than global frequency. The ASCII encoder script is also fixed, and the example trace used in the regressions is updated.
2016-02-23dev, arm: Implement the NoMali reset callbackAndreas Sandberg
Add a callback handler for the NoMali reset callback. This callback is called whenever the GPU is reset using the register interface or the NoMali API. The callback can be used to override ID registers using the raw register API.
2016-02-23dev, arm: Refactor the NoMali GPUAndreas Sandberg
Refactor and cleanup the NoMaliGpu class: * Use a std::map instead of a switch block to map the parameter enum describing the GPU type to a NoMali type. * Remove redundant NoMali handle from the interrupt callback. * Make callbacks and API wrappers protected instead of private to enable future extensions. * Wrap remaining NoMali API calls.
2016-02-23arm: Ship Linux device trees with gem5Andreas Sandberg
Ship aarch32 and aarch64 device trees with gem5. We currently ship device trees as a part of the gem5 Linux kernel repository. This makes tracking hard since device trees are supposed to be platform dependent rather than kernel dependent (Linux considers device trees to be a stable kernel ABI). It also makes code sharing between aarch32 and aarch64 impossible. This changeset implements a set of device trees for the new VExpress_GEM5_V1 platform. The platform is described in a shared file that is separate from the memory/CPU description. Due to differences in how secondary CPUs are initialized, aarch32 and aarch64 use different base files describing CPU nodes and the machine's compatibility property.
2016-02-23scons: Add missing override to appease clangAndreas Hansson
Make clang happy...again.
2016-02-18ruby: move range change send from RubyPort to derived classes.Tony Gutierrez
2016-02-18gpu: fix bugs with MemFence, Flat Instrs and Resource utilizationJohn Kalamatianos
Both Memory Fence is now flagged as Global Memory only to avoid resource oversubscribing. Flat instructions now check for Shared Memory resource busy to avoid oversubscribing resources. All WaitClass resources now use cycles (not ticks) to register the number of pipe stages between Scoreboard and Execute to be consistent with instruction scheduling logic which always used clock cycles.
2016-02-17gpu-compute: remove brig_object.hh from hsa_object.ccTony Gutierrez
brig_object.hh is specific to the HSAIL ISA, and hence should not be included in ISA-agnostic code.
2016-02-17ruby: send address ranges from RubyPortTony Gutierrez
2016-02-17scons: Enable building with the gcc/clang Address SanitizerAndreas Hansson
Allow the user to easily build gem5 with the Address Sanitizer, part of both gcc and clang these days.
2016-02-15misc: Add missing overrides to appease clangAndreas Hansson
Since the last round of fixes a few new issues have snuck in. We should consider switching the regression runs to clang.
2016-02-15mem: Avoid using invalid iterator in cache lock list traversalAndreas Hansson
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
2016-02-14ruby: make DMASequencer inherit from RubyPortMichael LeBeane
This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the parent class of DMASequencer. It removes redundant code and restores some features which were lost when directly inheriting from MemObject. For example, DMASequencer can now communicate to other devices using PIO, which is useful for memmory-mapped communication between multiple DMADevices.
2016-02-13configs: add command-line option to stop debug outputMichael LeBeane
This patch adds a --debug-end flag to main.py so that debug output can be stoped at a specified tick, while allowing the simulation to continue. It is useful in situations where you would like to produce a trace for a region of interest while still collecting stats for the entire run. This is in contrast to the currently existing --debug-break flag, which terminates the simulation at the tick.
2016-02-13syscall_emul: Implement clock_getres() system callMichael LeBeane
This patch implements the clock_getres() system call for arm and x86 in linux SE mode.
2016-02-10stats: Update stats to reflect changes to cache and crossbarAndreas Hansson
2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
Avoid being overly conservative in clearing load locks in the cache, and allow writes to the line if they are from the same context. This is in line with ALPHA and ARM.
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not.
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
This patch unifies the snoop handling in case of hitting writebacks with how we handle snoops hitting in the tags. As a result, we end up using the same optimisation as the normal snoops, where we inform the downstream cache if we encounter a line in Modified (writable and dirty) state, which enables us to avoid sending out express snoops to invalidate any Shared copies of the line. A few regressions consequently change, as some transactions are sunk higher up in the cache hierarchy.
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
2016-02-08scons: always generate sim/tags.ccCurtis Dunham
Due to insufficient build deps, the checkpoint tags might not get updated; this commit solves this. Due to the uncommon nature of the build target, regenerating tags.cc is a fairly clean solution. Since SCons hashes file contents, it won't recompile anything unless a new checkpoint upgrader is actually added. --HG-- extra : amend_source : ed3879da7668554693f697076deaf5029cc9b954
2016-02-06x86: revamp cmpxchg8b/cmpxchg16b implementationAlexandru Dutu
The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b.
2016-02-06arch, x86: add support for arrays as memory operandsSteve Reinhardt
Although the cache models support wider accesses, the ISA descriptions assume that (for the most part) memory operands are integer types, which makes it difficult to define instructions that do memory accesses larger than 64 bits. This patch adds some generic support for memory operands that are arrays of uint64_t, and specifically a 'u2qw' operand type for x86 that is an array of 2 uint64_ts (128 bits). This support is unused at this point, but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE memory accesses will also be rewritten to use this support. Support for 128-bit accesses could also have been added using the gcc __int128_t extension, which would have been less disruptive. However, although clang also supports __int128_t, it's still non-standard. Also, more importantly, this approach creates a path to defining 256- and 512-byte operands as well, which will be useful for eventual AVX support.
2016-02-06arch: get rid of dummy var initSteve Reinhardt
MemOperand variables were being initialized to 0 "to avoid 'uninitialized variable' errors" but these no longer seem to be a problem (with the exception of one use case in POWER that is arguably broken and easily fixed here). Getting rid of the initialization is necessary to set up a subsequent patch which extends memory operands to possibly not be scalars, making the '= 0' initialization no longer feasible.
2016-02-06syscall_emul: fix bug in aux vector initializationSteve Reinhardt
Writing 16 bytes from an 8-byte source value is a bad idea. This doesn't appear to have broken anything, but showed up as spurious differences when tracediffing runs.
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
2016-02-06util: fix apparent statetrace bugSteve Reinhardt
In the process of trying to eliminate boolean comparisons, I ran across this statement that appears to be a bug (should have been an assignment).
2016-02-06util: added line length and boolean comparison style checkersSteve Reinhardt
Added checkers for line length and boolean comparisons (== true/== false) to the style script.
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06util: clean up and extend style checkerSteve Reinhardt
Added a new Verifier object to check for and fix spacing between if/while/for and following paren. Restructured Verifier class to make it easier to add new subclasses, particularly by using a global list of verifiers to auto-generate command line options and simplify the invocation loop.
2016-02-06util: delete old unused style-checking scriptsSteve Reinhardt
The functions in these scripts were apparently folded into style.py but the old scripts were orphaned without being deleted. Get rid of them so their existence is no longer confusing.
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-02-06stats: update EIO stats for recent changesSteve Reinhardt
2016-02-04ext: fix SST connectorCurtis Dunham
Should work with SST 5.1 and trunk as of right now.
2016-01-29ext: remove redundant parameter in example SST+gem5 testCurtis Dunham
The SST connector automatically adds --initialize-only to the gem5 "command line" (as it should); the config script doesn't need it.
2016-01-29ext: Update NoMali to external rev f08e0a5Andreas Sandberg
Update NoMali from external revision 9adf9d6 to f08e0a5 and bring in the following changes: f08e0a5 Add support for tracking address space state f11099e Fix job slot register handling when running new jobs b28c98e api: Add a reset callback 29ac4c3 tests: Update gitignore to cover all future test cases 1c6b893 Propagate reset calls to all job slots 8f8ec15 Remove redundant reg vector in MMU 85d90d2 tests: Fix incorrect extern declaration
2016-01-22stats: update stats to after GPU checkinTony Gutierrez
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2016-01-22ruby: changed all references to numCPs to num-cpBrad Beckmann