| Age | Commit message (Expand) | Author |
|---|
| 2013-02-19 | x86: Move APIC clock divider to Python | Andreas Hansson |
| 2013-02-19 | mem: Fix SenderState related cache deadlock | Sascha Bischoff |
| 2013-02-19 | mem: Add predecessor to SenderState base class | Andreas Hansson |
| 2013-02-19 | base: Fix a bug in the address interleaving | Andreas Hansson |
| 2013-02-19 | mem: Ensure trace captures packet fields before forwarding | Andreas Hansson |
| 2013-02-15 | options: add command line option for dtb file | Anthony Gutierrez |
| 2013-02-15 | loader: add a flattened device tree blob (dtb) object | Anthony Gutierrez |
| 2013-02-15 | ext lib: add libfdt to enable flattened device tree support | Anthony Gutierrez |
| 2013-02-15 | stats: update regressions for o3 changes in renaming and translation. | Ali Saidi |
| 2013-02-15 | arm: fix a page table walker issue where a page could be translated multiple ... | Mrinmoy Ghosh |
| 2013-02-15 | cpu: Document exec trace flags | Andreas Sandberg |
| 2013-02-15 | dev: Use the correct return type for disk offsets | Andreas Sandberg |
| 2013-02-15 | cpu: Avoid duplicate entries in tracking structures for writes to misc regs | Geoffrey Blake |
| 2013-02-15 | cpu: Fix rename mis-handling serializing instructions when resource constrained | Geoffrey Blake |
| 2013-02-15 | ARM: Postpones creation of framebuffer output file until it is actually used. | Chris Emmons |
| 2013-02-15 | mem: Tighten up cache constness and scoping | Andreas Hansson |
| 2013-02-15 | base: Add warn() and inform() to m5.utils for use from python | Sascha Bischoff |
| 2013-02-15 | o3: fix tick used for renaming and issue with range selection | Matt Horsnell |
| 2012-10-25 | arm: Don't export private GIC methods | Andreas Sandberg |
| 2012-10-25 | arm: Create a GIC base class and make the PL390 derive from it | Andreas Sandberg |
| 2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-02-15 | config: Remove O3 dependencies | Andreas Sandberg |
| 2013-02-15 | config: Move CPU handover logic to m5.switchCpus() | Andreas Sandberg |
| 2013-02-15 | config: Cleanup CPU configuration | Andreas Sandberg |
| 2013-02-15 | cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy | Andreas Sandberg |
| 2013-02-15 | cpu: Add CPU metadata om the Python classes | Andreas Sandberg |
| 2013-02-15 | arm: fix some fp comparisons that worked by accident. | Ali Saidi |
| 2013-02-15 | cpu: include set in o3/commit_impl. | Ali Saidi |
| 2013-02-15 | ARM: Fix an issue with clang generating wrong code. | Ali Saidi |
| 2013-02-15 | cpu: fix case with o3 cpu blocking and unblocking decode in cycle | Ali Saidi |
| 2013-02-15 | cpu: Fix a livelock in the o3 cpu. | Ali Saidi |
| 2013-02-10 | base: Add support for newer versions of IPython | Andreas Sandberg |
| 2013-02-14 | Ruby: Fix compilation errors on gcc 4.7 and clang 3.2 | Andreas Hansson |
| 2013-02-10 | regressions: update stats due to changes to ruby | Nilay Vaish |
| 2013-02-10 | ruby: MI protocol: add a missing transition | Nilay Vaish |
| 2013-02-10 | ruby: enable multiple clock domains | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles (final patch in the series) | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in garnet fixed and flexible | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Tick in replacement policy classes | Nilay Vaish |
| 2013-02-10 | ruby: convert block size, memory size to unsigned | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in MessageBuffer | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in Memory Controller | Nilay Vaish |
| 2013-02-10 | ruby: Replace Time with Cycles in SequencerMessage | Nilay Vaish |
| 2013-02-10 | ruby: replace Time with Cycles in Message class | Nilay Vaish |
| 2013-02-10 | ruby: replaces Time with Cycles in many places | Nilay Vaish |
| 2013-02-10 | base: add some mathematical operators to Cycles class | Nilay Vaish |
| 2013-02-10 | ruby: modifies histogram add() function | Nilay Vaish |
| 2013-02-10 | ruby: record fully busy cycle with in the controller | Nilay Vaish |
| 2013-02-10 | base: Fix broken IPython argument handling | Andreas Sandberg |
