| Age | Commit message (Collapse) | Author |
|---|
|
switching between O3 and another CPU, O3's tick event might still be scheduled
in the event queue (as squashed). Therefore, check for a squashed tick event
as well as a non-scheduled event when taking over from another CPU and deal
with it accordingly.
|
|
to another in the Power ISA.
|
|
|
|
|
|
It would be nice if python had a tree class that would do this for real,
but since we don't, we'll just keep a sorted list of keys and update
it on demand.
|
|
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to
True, then imports that would normally find python code compiled into
the executable will instead first check in the absolute location where
the code was found during the build of the executable. This only
works for files in the src (or extras) directories, not automatically
generated files.
This is a developer feature!
|
|
|
|
This tidbit was pulled from a larger patch for Tim's sake, so
the comment reflects functions that haven't been exported yet.
I hope to commit them soon so it didn't seem worth cleaning up.
|
|
fault.
|
|
|
|
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
|
|
|
|
|
|
On Nate's advice, overload 'char' as well as 'signed char'
and 'unsigned char'.
|
|
(without requiring a leading underscore)
Also a little cleanup on type names in SimObject.py.
|
|
There used to be a reason to have StartupCallback
be a separate object, but not any more. Now
it's just confusing.
|
|
Move some static checkpoint stuff into the
Checkpoint object namespace.
|
|
Somehow we now need to explicitly specialize on
'signed char' and not just 'char' to catch cases
like int8_t
|
|
See comments in util/checkpoint-tester.py for details.
|
|
|
|
|
|
|
|
|
|
m5 doesnt do stats specific to binary and this resource request stat is probably only
useful for people who really know the ins/outs of the model anyway
|
|
|
|
the nextPC was getting sent to the branch predictor not the current PC, so
the RAS was returning the wrong PC and mispredicting everything.
|
|
replace priority queue with vector of lists(1 list per stage) and place inside a class
so that we have more control of when an instruction uses a particular schedule entry
...
also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the
wiki for details on this process
|
|
|
|
|
|
remove the annotation 'virtual' from function declaration that isnt being derived from
|
|
|
|
|
|
this applies to multithreading models which would like to squash a thread on memory stall
|
|
|
|
|
|
- use InOrderBPred instead of Resource for DPRINTFs
- account for DELAY SLOT in updating RAS and in squashing
- don't let squashed instructions update the predictor
- the BTB needs to use the ASID not the TID to work for multithreaded programs
- add stats for BTB hits
|
|
also, remove inst-req stats as default.good for debugging
but in terms of pure processor stats they aren't useful
|
|
remove stall only when necessary
add debugging printfs
|
|
use nextCycle to calculate ticks after addition
|
|
Thanks to Joe Gross for pointing this out (again?).
Apologies to anyone who pointed it out earlier and
we didn't listen.
|
|
the system pointers match in Full System mode.
|
|
Some subset of UpgradeReq messages shifted to the
new SCUpgradeReq type. Other than that there
are no significant differences.
|
|
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
|
|
Only set the dirty bit when we actually write to a block
(not if we thought we might but didn't, as in a failed
SC or CAS). This requires makeing sure the dirty bit
stays set when we get an exclusive (writable) copy
in a cache-to-cache transfer from another owner, which
n turn requires copying the mem-inhibit flag from
timing-mode requests to their associated responses.
|
|
|
|
|
|
|
|
|
|
|
|
|
