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AgeCommit message (Expand)Author
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can b...Gabe Black
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
2008-01-21X86: Fill out group17 in the decoder.Gabe Black
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
2008-01-16Update long o3 regressions for o3 change in previous changesetAli Saidi
2008-01-15Update O3 ref outputs: very minor stats change due to previous cset.Steve Reinhardt
2008-01-14The reason is that the event is supposed to put the instructions ready to exe...Ke Meng
2008-01-12X86: Redo the bit test instructions.Gabe Black
2008-01-12X86: Fix the wrmsr instruction.Gabe Black
2008-01-12X86: Make the effective segment base shadow the regular one, not the selector.Gabe Black
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ...Gabe Black
2008-01-12X86: Fix the general IO instructions dataSize.Gabe Black
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
2008-01-02Very minor memtest regression stats changes from recent coherence bug fixes.Steve Reinhardt
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
2008-01-01SPARC: Fix a bug where the TLB would match against the wrong entries.Gabe Black
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without stan...Ali Saidi
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context t...Ali Saidi
2007-12-11Fix minor bug in util/style.pySteve Reinhardt
2007-12-03X86: Update the parser reference output which has mysteriously changed again?Gabe Black
2007-12-03X86: Please excuse my dear Aunt Sally. (precedence bug)Gabe Black
2007-12-02X86: Make sure the memory index is calculated using the address size for bit ...Gabe Black
2007-12-02X86: Fix a copy/paste mistake where the bit test instructions were using an i...Gabe Black
2007-12-02X86: Make the page not present panic more descriptive.Gabe Black
2007-12-02X86: Start setting up the real mode data structure.Gabe Black
2007-12-02X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.Gabe Black
2007-12-01X86: Add in a missing "break".Gabe Black
2007-12-01X86: Actually do something for the MiscRegFile clear function.Gabe Black
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
2007-12-01X86: Add a missing microcode file to the sconscript.Gabe Black
2007-12-01X86: Fix a copy paste error in the bts microcode.Gabe Black
2007-12-01X86: Implement mov from control register.Gabe Black
2007-12-01X86: First crack at far returns. This is grossly approximate.Gabe Black
2007-12-01X86: Reorganize segmentation and implement segment selector movs.Gabe Black
2007-12-01X86: Make the "fault" microop predicated.Gabe Black
2007-12-01X86: Implement the LIDT instruction.Gabe Black
2007-12-01X86: Implement the lgdt instruction.Gabe Black
2007-12-01X86: Implement wrbase and wrlimit for loading pseudo descriptors.Gabe Black
2007-12-01X86: Separate the effective seg base and the "hidden" seg base.Gabe Black
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