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2006-08-22Commiting a version of the multi-phase snoop atomic bus so people can see ↵Ron Dreslinski
the framework. Doesn't work, but also doesn't break uni-processor systems. Working on pulling out the changes in the cache so that it remains working. src/mem/bus.cc: Changes for multi-phase snoop Some code for registering snoop ranges (a version that compiles and runs, but does nothing) src/mem/bus.hh: Changes for multi-phase snoop src/mem/packet.hh: Flag for multi-phase snoop src/mem/port.hh: Status for multi-phase snoop --HG-- extra : convert_revision : 4c2e5263bba16e3bcf03aabe36ff45ec36de4720
2006-08-22Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : ccbca1320471d809d25a6359b79d9f2d46c6ce73
2006-08-22Update refs for tru64 with initialized cache statsRon Dreslinski
--HG-- extra : convert_revision : 708553b57307c353d6a8e403dc1ed4deb6dd2dfb
2006-08-21Fix annulled unconditional branchesGabe Black
--HG-- extra : convert_revision : 698b0ce38c7a47306f97df2cc80cdae4a51b22c7
2006-08-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 46e14792cfd18e4e27935b848c9953a7c44e9334
2006-08-21SConstruct:Steve Reinhardt
Add checks for swig & libz, version check for swig. Factor out version check code into function, use for mysql too. SConstruct: Add checks for swig & libz, version check for swig. Factor out version check code into function, use for mysql too. --HG-- extra : convert_revision : a077d961ae52011141fbf5021b167485f8638139
2006-08-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 15d8fd51f0c70da4d2e52c11864f3ab0f3f62811
2006-08-21Update REFs for statistics patch in cacheRon Dreslinski
--HG-- extra : convert_revision : 8987d3ab62ea4b2fa18ebd40fc980b30561d7e45
2006-08-21Got rid of the aux_data array since it shouldn't have existed.Gabe Black
Added in the filename parameter which is provided for the user space linker. Fix the ordering and alignment of stack elements. Made mmap start with the address it has been seen starting with "in the wild" --HG-- extra : convert_revision : 8734753145f59a6cb433e4f92f43cb28a44b56d4
2006-08-21Fixed the parameters to memset. sizeof(regSegments[x]) may have been ↵Gabe Black
returning the size of a pointer to an IntReg --HG-- extra : convert_revision : 02c04ffceb447b7683ba5ebd4752819d0014cc19
2006-08-21Two bugs found by my tracing tool.Gabe Black
1. alignaddr wrote it's address to a floating point register rather than a gpr. 2. sethi was sign extending it's immediate value. --HG-- extra : convert_revision : 9aa30a6485bc4cba916367973b986d439b7c7588
2006-08-21Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem src/python/m5/objects/BaseCPU.py: Merge duplicate change --HG-- extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
2006-08-21Changes so that time in the packet is actually set properly.Ron Dreslinski
src/mem/packet.hh: Make sure packets set the time parameter correctly. --HG-- extra : convert_revision : e381d2789e0aaa1b6c2fbde417b7ba5815deec61
2006-08-21fs.py:Steve Reinhardt
Add temporary cpu.mem parameter settings. configs/example/fs.py: Add temporary cpu.mem parameter settings. --HG-- extra : convert_revision : d7c2fcd8df8dc809b0511485877b2a85769aaf43
2006-08-20TEST_CPU_MODELS isn't used anymore.Steve Reinhardt
--HG-- extra : convert_revision : 742bda87e79657573cec404b8650fa26d189d1a1
2006-08-20Add Alpha Linux version of "hello world" test.Steve Reinhardt
--HG-- extra : convert_revision : 22cd31c58f18fd92bd61ee4b4a218926f7290045
2006-08-20Alpha "hello world" test is really Tru64 not Linux... oops.Steve Reinhardt
--HG-- rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out => tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout rename : tests/test-progs/hello/bin/alpha/linux/hello => tests/test-progs/hello/bin/alpha/tru64/hello extra : convert_revision : 583c30603e51304c9a19e3ae25fbf0623be0489d
2006-08-20configs/example/fs.py:Steve Reinhardt
Arg to m5.simulate() is a delta, not an absolute curTick value. I didn't test this change, but I'm not convinced the previous example was tested either, so I don't feel too badly about it. configs/example/fs.py: Arg to m5.simulate() is a delta, not an absolute curTick value. I didn't test this change, but I'm not convinced the previous example was tested either, so I don't feel too badly about it. --HG-- extra : convert_revision : ef7df7b83b3e2b5da02408c674169ccbed75a441
2006-08-19SConscript:Steve Reinhardt
Fix BATCH_CMD bug. tests/SConscript: Fix BATCH_CMD bug. --HG-- extra : convert_revision : 696d51a67790506db749244edf4afab920a63d1b
2006-08-18Update reference outputsSteve Reinhardt
--HG-- extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd
2006-08-18Add caches in, fix cpu.mem paramSteve Reinhardt
--HG-- extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
2006-08-17Changes to build m5.fastSteve Reinhardt
--HG-- extra : convert_revision : 2ec600b8e72e40e8b96e3b1dbe0334aa05e0f30b
2006-08-17Add readfile back in.Kevin Lim
--HG-- extra : convert_revision : 0b64f2d95b439b19f1131fe00f45da56617b0026
2006-08-17Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/tmp/m5.newmem --HG-- extra : convert_revision : 49289cfe8d547045dd89133db71d16318bc8510b
2006-08-17add default range to PhysicalMemoryAli Saidi
--HG-- extra : convert_revision : 0a622ab0f0f7653d28d4ed3dd27113ae2bc82cae
2006-08-17SConstruct:Steve Reinhardt
rename build/*/test dir to build/*/tests for consistency SConstruct: rename build/*/test dir to build/*/tests for consistency --HG-- extra : convert_revision : 6af3cf6b2d6582b2c4d2bc9211e44767e0fa494f
2006-08-17AUTHORS:Lisa Hsu
minor change AUTHORS: minor change --HG-- extra : convert_revision : b638f14f0541ff5d48546c7fcd27d1bf0bdf615f
2006-08-17Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 382a9d4b420a9bdb35f93049306b7b7af0d33ad5
2006-08-17make tree rcS files reflect what we've been actually using in /dist.Lisa Hsu
also, update all the rcS files so that they are in sync with the new linux-dist build system. configs/boot/devtime.rcS: configs/boot/iscsi-client.rcS: configs/boot/iscsi-server.rcS: configs/boot/micro_memlat.rcS: configs/boot/micro_stream.rcS: configs/boot/micro_tlblat.rcS: configs/boot/nat-netperf-maerts-client.rcS: configs/boot/nat-netperf-server.rcS: configs/boot/nat-netperf-stream-client.rcS: configs/boot/nat-spec-surge-client.rcS: configs/boot/nat-spec-surge-server.rcS: configs/boot/natbox-netperf.rcS: configs/boot/natbox-spec-surge.rcS: configs/boot/netperf-rr.rcS: configs/boot/netperf-server.rcS: configs/boot/netperf-stream-client.rcS: configs/boot/netperf-stream-nt-client.rcS: configs/boot/nfs-client-nhfsstone.rcS: configs/boot/nfs-client-tcp-smallb.rcS: configs/boot/nfs-client-tcp.rcS: configs/boot/nfs-client.rcS: configs/boot/nfs-server-nhfsstone.rcS: configs/boot/nfs-server.rcS: configs/boot/ping-client.rcS: configs/boot/ping-server.rcS: configs/boot/spec-surge-client.rcS: configs/boot/spec-surge-server.rcS: configs/boot/surge-client.rcS: configs/boot/surge-server.rcS: make tree rcS files reflect what we've been actually using in /dist. --HG-- extra : convert_revision : 48fe4fe71938ef9d029e428028a271242c8d2faa
2006-08-16we don't want the old memory timing dram model eitherAli Saidi
--HG-- extra : convert_revision : 7de51b1e42cff8c0f377a21cfcb6d1d13df1847a
2006-08-16Fix the caches not working in the regressionRon Dreslinski
src/python/m5/objects/BaseCPU.py: Make mem parameter a MemObject, not just a PhysicalMemory Fix a reference not using self tests/configs/simple-atomic.py: Set the mem paramter tests/configs/simple-timing.py: Set the mem parameter --HG-- extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
2006-08-16Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/tmp/m5.newmem --HG-- extra : convert_revision : b754945635cc0864fdd68ec4bee736aab9bca407
2006-08-16DRAM Memory doesn't crash the simulator now.. still untested.Ali Saidi
--HG-- extra : convert_revision : fa2d2c5ec4073383f1b2b2f466d0245f2d6a6c35
2006-08-16we don't want the splash2 config files either, they haven't been converted yetAli Saidi
--HG-- extra : convert_revision : 09adadca1ead8d32589cf7a243fddd24fcc51f4b
2006-08-16Add checkpointing and configuration stuff to the people that worked on itNathan Binkert
--HG-- extra : convert_revision : 565f0144d3aa6194665e49e3b0ad314c5d671bba
2006-08-16Added in SPARC ISA specifically. Thanks to whoever fleshed out my entry.Gabe Black
--HG-- extra : convert_revision : acb123227c7efbb46cc25e0ca69f7b2e2ec5b9c1
2006-08-16add etherdump file optionAli Saidi
--HG-- extra : convert_revision : 6b62398778208bc4e64582e06fb73b71a94f3014
2006-08-16Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/tmp/m5.newmem --HG-- extra : convert_revision : f4fa62290ca2bbd4726fb6c8e89655dade53bb68
2006-08-16Fix Physical Memory to allow memory sizes bigger than 128MB.Ali Saidi
Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses causes a simulator segfault. src/SConscript: Add dram.cc to sconscript src/mem/physical.cc: src/mem/physical.hh: Add params struct to physical memory, use params, make latency function be virtual src/python/m5/objects/PhysicalMemory.py: Add DRAMMemory python class --HG-- extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d
2006-08-16Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : 3bf1742201e61d61a906d057b52dc158aa7be2d0
2006-08-16More regression updates.Steve Reinhardt
Get rid of caches in simple-timing config for now. tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) --HG-- extra : convert_revision : 472030f63297346976db6274a78235c93d4eef8e
2006-08-16Add in checkpointing in the frontend, so that when a checkpoint is called, ↵Lisa Hsu
the python handles it, and the simulation continues. Also, make it so that the cycle number is part of the cpt dir name, so that multiple checkpoints do not overwrite each other. --HG-- extra : convert_revision : a55e4ac20da5a57ea8735951b9070960b9b8298f
2006-08-16Minor regression fixes.Steve Reinhardt
src/python/m5/objects/BaseCPU.py: bug fix tests/SConscript: fix up diff ignore strings to reflect changes in m5 output --HG-- extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128
2006-08-16AUTHORS:Korey Sewell
fix 'reorganization' typo and added o3cpu multiple isa support to list AUTHORS: fix 'reorganization' typo and added o3cpu multiple isa support to list --HG-- extra : convert_revision : cd5d0ba69b37add0f10135e5772a57a7aacdf06e
2006-08-16Tweak my author listRon Dreslinski
--HG-- extra : convert_revision : ab79756d1c7fb4f8bfde86ef396597856a7ceb54
2006-08-16Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 659f84c883b9992ae48f26c837983b9f8fcf18ab
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski
src/cpu/o3/fetch_impl.hh: Fix ordering so dereference works src/cpu/o3/lsq_impl.hh: Check to make sure we didn't squash already src/cpu/o3/lsq_unit.hh: Fix for counting squashed retrys in the WB count src/cpu/o3/lsq_unit_impl.hh: Make sure to set retryID for stores, and clear it appropriately --HG-- extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
2006-08-16Fixes for blocking in the caches that needed to be pulledRon Dreslinski
src/mem/cache/base_cache.cc: Add in retry path for blocking with multi-level caches src/mem/cache/base_cache.hh: Pull more of the blocking fixes into head src/mem/packet.hh: Fix typo --HG-- extra : convert_revision : d4d149adfa414136ebd2c4789b739bb065710f7a
2006-08-16Add ppls contributions from looking at Authors header... Probably missed ↵Ali Saidi
stuff so look it over. Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/tmp/m5.newmem AUTHORS: merge kevin's changes in --HG-- extra : convert_revision : 86344b6d89d90ec7002584d48736e29a9a3c72e5
2006-08-16I threw together the authors file from looking at the Authors of files.Ali Saidi
Feel free to change as you see fit AUTHORS: I threw together the authors file from looking at the Authors of files --HG-- extra : convert_revision : c13b52c60bbc429b29c64b5bebf5bf4971274a8d
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 11:16:07 +0000