Age | Commit message (Collapse) | Author |
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extra : convert_revision : dd6b4d14070a2e99c179c5f780c9935847da8eda
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The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.
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what this is for, and it probably doesn't work on anything but Alpha.
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Alpha does.
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object?
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from some other include.
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extra : convert_revision : adbd4899508e3d30959a504a48402f01d1187099
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
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src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
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extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
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configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy
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extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
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configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
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nonsensical for x86.
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non-sensical in x86.
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into iceaxe.int.chaotic.net:/Users/nate/work/m5/outgoing
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32
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extra : convert_revision : bbd0def502e423e64e2c4f6415a4b043b60c7f90
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so things are organized in a more sensible manner. Take apart
finalInit and expose the individual functions which are now
called from python. Make checkpointing a bit easier to use.
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lseek syscall.
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with SPARC.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
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extra : convert_revision : dcb1fc0c6252fb96a956640c6d7995679da725e5
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as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
make ldtw(a) Twin 32 bit load work correctly
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32
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extra : convert_revision : 88d1401f6e6b7c82344abef2c81b3c22bf6a0499
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call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
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extra : convert_revision : ea873f01c62234c0542f310cc143c6a7c76ade94
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removed from the other ones as well.
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extra : convert_revision : 0c07534de42d6c32ac26d9e43709111e3ab30d57
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or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3"
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extra : convert_revision : f4f1d3fd0fb28468b0ee507aaadf3c14aa9cf924
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
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extra : convert_revision : 7e8c3572ede7d93910fc3e2a2e76d9a38b1f4243
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
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src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
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