summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2006-11-02Implement device that will return BadAddress.Kevin Lim
--HG-- extra : convert_revision : d833c20f691e01c84a0678f19f7d83f3ee50c0c1
2006-11-02Caches return a new functional port whenever asked for one.Kevin Lim
src/mem/cache/base_cache.cc: Have caches return a new functional port whenever asked for them. I'm pretty sure this is desired behavior. Ron can correct me if it's not. --HG-- extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
2006-11-02More proper handling of the ports.Kevin Lim
src/cpu/simple_thread.cc: Fix up port handling to share code. src/cpu/thread_state.cc: Separate code off into a function. src/cpu/thread_state.hh: Make a separate function that will get the CPU's memory's functional port. --HG-- extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
2006-11-02Remove function that should have been deleted.Kevin Lim
src/cpu/simple_thread.cc: This function should have been deleted from an earlier push. src/cpu/simple_thread.hh: Delete this function; it's now in thread_state.hh/.cc. --HG-- extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
2006-11-02Use ISA specific makeExtMI.Kevin Lim
src/arch/alpha/utility.hh: For now makeExtMI will be specific to the ISA. --HG-- extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-10-31Fix up configs.Kevin Lim
configs/common/Simulation.py: Remove mem parameter. configs/example/se.py: Remove debug output that got included in my other push. --HG-- extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
2006-10-31Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix configs/example/fs.py: configs/example/se.py: src/mem/tport.hh: Hand merge. --HG-- extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ↵Kevin Lim
for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31Ports now have a pointer to the MemObject that owns it (can be NULL).Kevin Lim
src/cpu/simple/atomic.hh: Port now takes in the MemObject that owns it. src/cpu/simple/timing.hh: Port now takes in MemObject that owns it. src/dev/io_device.cc: src/mem/bus.hh: Ports now take in the MemObject that owns it. src/mem/cache/base_cache.cc: Ports now take in the MemObject that own it. src/mem/port.hh: src/mem/tport.hh: Ports now optionally take in the MemObject that owns it. --HG-- extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 42712a50ca46ebc891b78186f4b6d1412a35d374
2006-10-31remove connectAll() and connect() code since it isn't used anymore. (The ↵Ali Saidi
python does it all) --HG-- extra : convert_revision : e16a1ff59d4522703b155c2e68379a3072e8f47f
2006-10-31add the ability to insert into the middle of the timing port send listAli Saidi
--HG-- extra : convert_revision : 5422025f74ba7013f98d1d1dcbd1070f580aae61
2006-10-30Delete obsolete directories: src/oldmem, src/mem/timing, src/mem/NOTES.Steve Reinhardt
--HG-- extra : convert_revision : 948b4aaf484f7f7c2fce16201cd51ecb111af7d4
2006-10-30FSConfig.py:Lisa Hsu
Accidentally committed this last time configs/common/FSConfig.py: Accidentally committed this last time --HG-- extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
2006-10-30se.py, fs.py:Lisa Hsu
import Caches Simulation.py: Fix typo - L2Cache --> L1Cache configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches --HG-- extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
2006-10-30ensure that there is a "/" between the cptdir and the cpt.%d.Lisa Hsu
--HG-- extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
2006-10-30Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 836fcb45f399ed4f860be2d0bfe2ac4709bfe2ef
2006-10-30decouple the switch option from the warmup period option - parsing was ↵Lisa Hsu
confused otherwise, oops. --HG-- extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
2006-10-30Use some python os.path stuff to make it more flexible where we can execute ↵Kevin Lim
this script from. --HG-- extra : convert_revision : a76861a0f2669a7cd3bf3a34177739c69a913545
2006-10-30Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : ce5f394a4a62f7452b9631763425f65b911387bb
2006-10-30add some comments and make the warmup period in a switchover parameterizable.Lisa Hsu
configs/common/Options.py: make the warmup period in a standard switch part of the option. configs/common/Simulation.py: add some comments and also make the warmup period an option. --HG-- extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
2006-10-29An attempt to serialize the state of the micro code mechanism in the simple cpu.Gabe Black
src/cpu/simple/base.cc: Make a microcoded op start at the current micropc, rather than starting at 0. src/cpu/thread_state.cc: Serialize the microPC and nextMicroPC --HG-- extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
2006-10-29Move the mem classes into util.isa so that multiple inheritance can be used ↵Gabe Black
in the future for micro insts. --HG-- extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29Fix when the IsDelayedCommit flag is set.Gabe Black
--HG-- extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
2006-10-29Bring casa and casxa up to dateGabe Black
src/arch/sparc/isa/decoder.isa: Fix up the casa and casxa instructions. src/arch/sparc/isa/formats/formats.isa: This is handled in loadstore.isa now src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version. src/arch/sparc/isa/formats/mem/mem.isa: The cas format is handled in loadstore.isa as well now. src/arch/sparc/isa/formats/mem/util.isa: Reorganized things a bit to better support cas --HG-- extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
2006-10-29Fixed ldstub to use the right format, and made the load/store operations use ↵Gabe Black
the integer microcode register. --HG-- extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
2006-10-29Add an integer microcode register.Gabe Black
--HG-- extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-28Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
2006-10-28remove intel nic from SConscriptAli Saidi
--HG-- extra : convert_revision : b01bb258c97cf42d46a94faedab31726623fe437
2006-10-28This one really needs to be arch/faults.hhGabe Black
--HG-- extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
2006-10-28Include the right version of faults.hhGabe Black
--HG-- extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
2006-10-28Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 9883fb35fd9c36e1819153f9976f8bdc73dbe8f3
2006-10-28One last adjustment to get rid of skew in the simple atomic cpu.Gabe Black
--HG-- extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
2006-10-27Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem configs/example/fs.py: configs/example/se.py: hand merge --HG-- extra : convert_revision : 13d248add87ac373d2653bb42adf4ac065f75ce3
2006-10-27factor out common run code from se.py and fs.py.Lisa Hsu
configs/example/fs.py: factor out common code. configs/example/se.py: factor out common code --HG-- extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
2006-10-27Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : b8b8a4428b2462d2df600e2ec7a9014a08246df8
2006-10-27add packet_access.hhAli Saidi
--HG-- extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
2006-10-27A more complete attempt to fix the clock skew.Gabe Black
--HG-- extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
2006-10-27Potential fix to clock skew problem.Gabe Black
--HG-- extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
2006-10-27Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
2006-10-27Update stats for fill/spill handlersGabe Black
--HG-- extra : convert_revision : 2ed2e868ccbb3316f84ea691497d2e0dd4ec2416
2006-10-27Got rid of some outdated comments.Gabe Black
--HG-- extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
--HG-- extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27Clean up MiscRegFileGabe Black
--HG-- extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-26Reorganized the MiscRegFileGabe Black
--HG-- extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
2006-10-26Cleaned up the decoder slightly.Gabe Black
--HG-- extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-26Added a few functions to stuff values into bitfields in an instruction.Gabe Black
--HG-- extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
--HG-- extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
2006-10-26Got rid of some debug outputGabe Black
--HG-- extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
--HG-- extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-19 14:51:18 +0000