Age | Commit message (Collapse) | Author |
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do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move.
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extra : convert_revision : 4c904c964678529c72b8f1044dfcb400604f6654
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because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer.
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extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
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an existing buffer.
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extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
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start fetching from.
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extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
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predicted taken or not.
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extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
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extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
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split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed
To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.
Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.
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extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
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(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
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extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
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(instead of complaining and exiting).
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extra : convert_revision : 24ac0bab7fd92d9e74c80847a667f0affcd0473d
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there was a fault prior to translation).
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extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
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extra : convert_revision : c961d1bf2acaae6807870b78f444a4a606be65cc
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extra : convert_revision : cac6e9d447675805e3fcc4342e3bfdbef179fbf5
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extra : convert_revision : e03634b5ec6b3c855c463618968984b5df7782f9
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Runtimes are way too long with current inputs.
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extra : convert_revision : 19323308b40fb7de00c77ee552e39ca6558804b8
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
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extra : convert_revision : 7c78ae3298645aed2179ed4f2aa361619406f9de
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extra : convert_revision : 9776806b24da70b815280e47d2d5ec8674c82669
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into vm1.(none):/home/stever/bk/newmem-cache2
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extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
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extra : convert_revision : 04f9131258bfb7cca1654e00273edb29bde2366b
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gracefully.
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extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
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and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit.
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extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
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extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
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architecture defined setSyscallReturn function instead of a duplicate copy.
src/cpu/o3/alpha/cpu.hh:
Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
Moved the tlbs to the base o3 cpu.
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extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
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RegFile *.
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extra : convert_revision : 5ed79ed18e443118a28d6890327c55a6a3fcd325
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/cpu/o3/commit_impl.hh:
Hand Merge
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extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
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src/cpu/o3/thread_context_impl.hh:
Use flattened indices
src/cpu/simple_thread.hh:
Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
The SyscallReturn class is no longer in arch/syscallreturn.hh
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extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
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extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
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setSyscallReturn function rather than having a duplicated one.
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extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
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architectural one.
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extra : convert_revision : 757866ad7a3c8be7382e1ffa71c60bc00c861f6f
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will break the checker!
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extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
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extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
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here that shouldn't be in the architecture specific DynInst classes.
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extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
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extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
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registers, and moved the flattenIndex function into the register file.
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extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
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extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
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result of a store conditional.
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extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
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