Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
configs/example/fs.py:
configs/example/se.py:
hand merge
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extra : convert_revision : 13d248add87ac373d2653bb42adf4ac065f75ce3
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configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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into zed.eecs.umich.edu:/z/hsul/work/m5/clean
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make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.
configs/example/se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.
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into zeep.pool:/z/saidi/work/m5.newmem.head
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scan all packets on a functional access.
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src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
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instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction.
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src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
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src/mem/packet.cc:
Copy size is calculated by END-BEGIN not BEGIN-END
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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configs/example/fs.py:
configs/example/se.py:
warm up of 1B CPU cycles
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
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1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
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1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.
configs/example/fs.py:
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
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with the timing cpu
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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memory operations in the SPARC ISA description.
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rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
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<inttypes.hh>
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