Age | Commit message (Collapse) | Author |
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into vm1.(none):/home/stever/bk/newmem-llsc
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src/sim/faults.cc:
Fix fault message.
src/kern/tru64/tru64.hh:
Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
Add print statement so we know what the faulting address is in SE mode.
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extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
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Note that command line syntax has totally changed as a result.
See comments for more details.
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into iceaxe.:/Volumes/work/research/m5/incoming
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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configs/splash2/run.py:
Update the splash2 file
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running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started. Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/tport.cc:
Merge PacketPtr changes
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extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
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Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
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and call it packet_access.hh and fix the #includes so
things compile right.
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util/term/term.c:
Reindent.
util/term/term.c:
Assume localhost if only port number is given on command line.
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extra : convert_revision : 768e61a56339a0795ca258cca788e9a2c20cbaae
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I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
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extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
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that we could test it.
src/cpu/memtest/memtest.cc:
Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
Fix cache to handle functional accesses properly based on memtester changes
Still need to fix functional accesses in timing mode now that the memtester can test it.
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extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
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?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
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extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
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Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
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Mark as satisfied for functional snoops.
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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that tracing gets turned on as the very first thing
in the selected cycle (tick).
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configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
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extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
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to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
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Factor out some asserts that were on both
sides of an if/else.
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extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
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Reindent due to resulting changes in nesting.
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but not on zizzer... g++ 4 thing maybe?)
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configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
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extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
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things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
add code to serialize/unserialize process
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extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
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writebacks delete the packet.
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