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AgeCommit message (Expand)Author
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-07-20x86: x86 instruction-implementation bug fixesDavid Hashe
2015-07-20util: added .cl OpenCL extension to file_type.pyBrad Beckmann
2015-07-20util: added .mk makefile extension to file_types.pyBrad Beckmann
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
2015-07-20syscall: Add readlink to x86 with special case /proc/self/exeDavid Hashe
2015-07-20ruby: add useful dprints to sequencerBrad Beckmann
2015-07-20slicc: isinstance bugfixDavid Hashe
2015-07-31util: add a vimrc that matches gem5 style guideAnthony Gutierrez
2015-07-31stats: Update switcheroo reference statsAndreas Sandberg
2015-07-31cpu: Update debug message from Fetch1 isDrained() in MinorAndreas Sandberg
2015-07-31cpu: Fix Minor drain issues when switched outAndreas Sandberg
2015-07-30stats: Bump stats after Minor switcheroo inclusionAndreas Sandberg
2015-07-30tests: Add Minor to the ARM full switcheroo testsAndreas Sandberg
2015-07-30cpu: Only activate thread 0 in Minor if the CPU is activeAndreas Sandberg
2015-07-30cpu: Fix drain issues in the Minor CPUAndreas Sandberg
2015-07-30stats: Update stats for clean eviction additionAndreas Hansson
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
2015-07-30mem: Tidy up packetAndreas Hansson
2015-07-30stats: Bump stats to match current behaviourAndreas Hansson
2015-07-30cpu: Fix issue identified by UBSanAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-24style: change Process function calls to use camelCaseBrandon Potter
2015-07-24syscall_emul: standardized file descriptor name and add return checks.Brandon Potter
2015-07-24base: refactor process class (specifically FdMap and friends)Brandon Potter
2015-07-24syscall_emul: file descriptor interface changesBrandon Potter
2015-07-24ruby: dma sequencer: removes redundant codeBrandon Potter
2015-07-22ruby: network: NetworkLink inherits from Consumer now.Nilay Vaish
2015-07-21configs: network test: remove redundant physical memoryNilay Vaish
2015-07-18stats: x86: updates due to patch on vexNilay Vaish
2015-07-17x86: decode instructions with vex prefixNilay Vaish
2015-07-15dev: add support for multi gem5 runsGabor Dozsa
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-07-13mem: Updated DRAMSim2 wrapper to new drain APIAndreas Hansson
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
2015-07-10ruby: replace g_ruby_start with per-RubySystem m_start_cycleBrandon Potter
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-07dev, arm: Add a device model that uses the NoMali modelAndreas Sandberg
2015-07-07ext: Add the NoMali GPU no-simulation libraryAndreas Sandberg
2015-07-07stats: Update pc-switcheroo statsAndreas Sandberg
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Move mem(Writeback|Invalidate) to SimObjectAndreas Sandberg
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