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Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
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caches.
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
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We're solely using SCons now.
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network performance
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dev/ns_gige.cc:
Clean up the interrupt code. Do a better job determining when
coalescing should happen.
Remove some bogus comments
Stop using magic numbers in initialization and comment what
the various numbers do
dev/ns_gige_reg.h:
#define describing which interrupts cannot be delayed and
which interrrupts we don't implement
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Make the database creation/removal/cleanup code use python
Make formulas work with the database
Add support to do some graphing, but needs more work
Still need to work on vectors, 2d vectors, dists and vectordists
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shared build and one for the per-config header file
copying.
SConscript:
Just include libelf/SConscript-local.
build/SConstruct:
Include libelf/SConscript-global.
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Change mode to -rwxrwx--x
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SConscript:
Add pyconfig/{pyconfig,code}.cc
Add list of object description (.od) files.
Include pyconfig/SConscript.
base/inifile.cc:
Get rid of CPP_PIPE... it never really worked anyway.
base/inifile.hh:
Make load(ifstream&) method public so pyconfig
code can call it.
sim/main.cc:
Handle Python config scripts (end in '.py' instead of '.ini').
sim/pyconfig/m5configbase.py:
Add license.
Fix minor __setattr__ problem (2.3 related?)
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rename : util/config/m5configbase.py => sim/pyconfig/m5configbase.py
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headers get created in build tree (under build/FOO/libelf)
instead of source tree (m5/libelf).
SConscript:
Move libelf/SConscript include here.
build/SConstruct:
Get rid of libelf/SConscript include (moved to
m5/SConscript).
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util/ccdrv/devtime.c:
coding style
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a p4 memory/cpu config
arch/alpha/alpha_memory.cc:
Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
Added m5debug break and m5switchcpu (the latter doesn't work)
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base/stats/events.cc:
Make this compile with MYSQL stuff
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space in tsunami.
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SConscript:
Added printk to scons
kern/linux/linux_system.cc:
kern/linux/printk.cc:
Forgot to commit this dprintk change
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SConscript:
grrr, spent half an hour looking for why the linker was dying. needed to include the new file printk.cc
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arch/alpha/ev5.hh:
Added max address PAL code can be at
arch/alpha/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
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dev/ns_gige.cc:
Make all DPRINTF statements take one line. If they need two lines,
break them up into separate statements. This makes grep much more
effective since *every* line will be prefixed by the cycle that the
trace message is from and the object that caused the message.
normalize some debugging statements so that searching is easier
(e.g. always say rxState, not rx state or receive state)
break into the debugger when a packet is dropped since we don't really
like dropping packets.
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whether or not the state machine is enabled rather than tracking the
specific instance of trying to halt the state machine.
dev/ns_gige.cc:
change back to tracking the state machine's enableness instead of
whether or not it is trying to halt. Also fix a major bug that
would cause the NIC to drop packets when the rx state machine was
idle, but enabled.
Fix a couple other bugs in the state machine where the idle interrupt
would happen at the wrong time.
Add a warning to deal with improper values of intrTick
dev/ns_gige.hh:
We need to keep track of whether the state machine is enabled
or not separately from the control register since the bits don't
always reflect the truth.
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dev/ns_gige.cc:
use the new PhysicalMemory dma_read and dma_write functions
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the user to choose which objects will break (so you can have only
the client system break for example.) Add features to differentiate
between breaking on reads and writes and break when an address gets
a specific data value.
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be more easily re-used. This currently uses some cooked up matching
function that I wrote a while ago, but should probably be changed
to use regular expressions in the future.
add doDebugBreak to control breakpoints on a per SimObject basis
SConscript:
add match
base/stats/events.cc:
base/trace.cc:
Move the object matching code into a separate file so it can be
more easily shared
base/trace.hh:
the object matching code was wrapped up and moved. adapt.
sim/sim_object.cc:
add the doDebugBreak flag that can be set on a per-SimObject
basis. This will be used in the future to control whether or
not debug_break() will actually break for a given object.
provide a function interface that can be called from the debugger.
sim/sim_object.hh:
add the doDebugBreak flag that can be set on a per-SimObject
basis. This will be used in the future to control whether or
not debug_break() will actually break for a given object.
--HG--
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the object name on every line.
This makes grep a bit more effective.
kern/tru64/dump_mbuf.cc:
use the new data dump format that trace.hh now provides
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Put correct date in copyright headers based on bk changesets
LICENSE:
Updated copyright on license file
README:
Updaded readme to reflect shift to scons and linux support
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
updated copyright (only changeset in 2004)
kern/kernel_stats.cc:
kern/kernel_stats.hh:
updated copyright
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base/mysql.cc:
Move the query function to the cc file
make the trace stuff work
base/mysql.hh:
Move the query function to the cc file
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/current
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base/mysql.hh:
Trace sql queries
base/traceflags.py:
Add a trace flag to trace sql queries
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Make it so the two system config can have one system with
a cache hier and the other without
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machine too. The fifo may have been full and we want
to get another packet into it if we can.
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add a function that can be called from the debugger to dump
the event queue
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and to do proper dumping of non-binned stats.
base/stats/mysql.cc:
have configure return whether or not the stat is a printable
stat. This avoids naming problems in the database.
don't store non printable stats.
dump non-binned stats into the special bin 0
base/stats/mysql.hh:
have configure return whether or not the stat is a printable
stat. This avoids naming problems in the database.
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and actually default to only storing a max of 96 bytes per
packet since that should be plenty to fit all of the headers in.
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base/statistics.cc:
add more checking to the stats stuff to make sure that
things are set up correctly
base/stats/statdb.cc:
Check that bins are only registered once.
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