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2013-04-17ruby: moesi cmp directory: add copyright noticeNilay Vaish
2013-04-17config: ruby network test: remove piobus checkNilay Vaish
2013-04-16stats: Bump the vortex stats to match latest behaviourAndreas Hansson
This patch bumps the stats for the failing vortex o3 regression.
2013-04-09stats: Bump Ruby stats for new changesetsJoel Hestness
The new changeset that can reorder Ruby profilers will cause the ruby.stats files to reordered statistics (the point of the patch). Update the references to ensure that these changes are reflected in regressions.
2013-04-09Configs: Fix handling of maxtick and take_checkpointsJoel Hestness
In Simulation.py, calls to m5.simulate(num_ticks) will run the simulated system for num_ticks after the current tick. Fix calls to m5.simulate in scriptCheckpoints() and benchCheckpoints() to appropriately handle the maxticks variable.
2013-04-09Ruby: Fix RubyPort evict packet memory leakJoel Hestness
When using the o3 or inorder CPUs with many Ruby protocols, the caches may need to forward invalidations to the CPUs. The RubyPort was instantiating a packet to be sent to the CPUs to signal the eviction, but the packets were not being freed by the CPUs. Consistent with the classic memory model, stack allocate the packet and heap allocate the request so on ruby_eviction_callback() completion, the packet deconstructor is called, and deletes the request (*Note: stack allocating the request causes double deletion, since it will be deleted in the packet destructor). This results in the least memory allocations without memory errors.
2013-04-09Ruby: Delete packet requests during warmupJoel Hestness
When warming up caches in Ruby, the CacheRecorder sends fetch requests into Ruby Sequencers with packet types that require responses. Since responses are never generated for these CacheRecorder requests, the requests are not deleted in the packet destructor called from the Ruby hit callback. Free the request.
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
This allows you to have (i.e.) an L2 cache that is not named "L2Cache" but is still a GenericMachineType_L2Cache. This is particularly helpful if the protocol has multiple L2 controllers.
2013-04-09Ruby: Order profilers based on versionJoel Hestness
When Ruby stats are printed for events and transitions, they include stats for all of the controllers of the same type, but they are not necessarily printed in order of the controller ID "version", because of the way the profilers were added to the profiler vector. This patch fixes the push order problem so that the stats are printed in ascending order 0->(# controllers), so statistics parsers may correctly assume the controller to which the stats belong.
2013-04-09Ruby: More descriptive message buffer connection fatalJason Power
When connecting message buffers between Ruby controllers, it is easy to mistakenly connect multiple controllers to the same message buffer. This patch prints a more descriptive fatal message than the previous assert statement in order to facilitate easier debugging.
2013-04-09Ruby: Fix typo in Slicc if-statement AST errorJason Power
The error in the SLICC code was hidden by the python error in SLICC parser before this patch
2013-04-07Ruby System, Cache Recorder: Use delete [] for trace varsJoel Hestness
The cache trace variables are array allocated uint8_t* in the RubySystem and the Ruby CacheRecorder, but the code used delete to free the memory, resulting in Valgrind memory errors. Change these deletes to delete [] to get rid of the errors.
2013-04-02rcs scripts: remove bbench.rcSAnthony Gutierrez
this run script shouldn't be used; bbench-ics.rcS or bbench-gb.rcS should be used instead.
2013-03-29regressions: updates due to changes to o3 cpu, x86 memory mapNilay Vaish
2013-03-29o3cpu: commit: changes interrupt handlingNilay Vaish
Currently the commit stage keeps a local copy of the interrupt object. Since the interrupt is usually handled several cycles after the commit stage becomes aware of it, it is possible that the local copy of the interrupt object may not be the interrupt that is actually handled. It is possible that another interrupt occurred in the interval between interrupt detection and interrupt handling. This patch creates a copy of the interrupt just before the interrupt is handled. The local copy is ignored.
2013-03-28x86: changes to apic, keyboardNilay Vaish
It is possible that operating system wants to shutdown the lapic timer by writing timer's initial count to 0. This patch adds a check that the timer event is only scheduled if the count is 0. The patch also converts few of the panics related to the keyboard to warnings since we are any way not interested in simulating the keyboard.
2013-03-28x86: create space in bios memory mapNilay Vaish
As of now, we mark the top 1MB of memory space as unusable. Part of it is actually usable and is required to be marked so by some of the newer versions of linux kernel. This patch marks the top 639KB as usable. This value was chosen by looking at QEMU's output for bios memory map.
2013-03-28regressions: update eio stats due to cache latency fixNilay Vaish
2013-03-27regressions: update due to cache latency fixNilay Vaish
2013-03-27mem: Fix cache latency bugMitch Hayenga
Fixes a latency calculation bug for accesses during a cache line fill. Under a cache miss, before the line is filled, accesses to the cache are associated with a MSHR and marked as targets. Once the line fill completes, MSHR target packets pay an additional latency of "responseLatency + busSerializationLatency". However, the "whenReady" field of the cache line is only set to an additional delay of "busSerializationLatency". This lacks the responseLatency component of the fill. It is possible for accesses that occur on the cycle of (or briefly after) the line fill to respond without properly paying the responseLatency. This also creates the situation where two accesses to the same address may be serviced in an order opposite of how they were received by the cache. For stores to the same address, this means that although the cache performs the stores in the order they were received, acknowledgements may be sent in a different order. Adding the responseLatency component to the whenReady field preserves the penalty that should be paid and prevents these ordering issues. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-03-27scons: don't die on warnings in swig-generated codeSteve Reinhardt
There's not much to do about it other than disable the offending warning anyway, so it's not worth terminating the build over. Also suppress uninitialized variable warnings on gcc (happens at least with gcc 4.4 and swig 1.3.40).
2013-03-26util: Add a utility script for decoding packet tracesAndreas Hansson
This patch adds a simple Python script that reads the protobuf-encoded packet traces (not gzipped), and prints them to an ASCII trace file. The script can also be used as a template for other packet output formats.
2013-03-26util: Add a utility script for encoding packet tracesAndreas Hansson
This patch adds a simple Python script that reads a simple ASCII trace format and encodes it as protobuf output compatible with the traffic generator. The script can also be used as a template for other packet input formats that should be converted to the gem5 packet protobuf format.
2013-03-26stats: Update stats for cache retry event checkAndreas Hansson
This patch updates the stats for the affected stats. All the changes are minimal (in the <0.01% range).
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
This patch solves the corner case scenario where the sendRetryEvent could be scheduled twice, when an io device stresses the IOcache in the system. This should not be possible in the cache system.
2013-03-26stats: Update stats to reflect bus retry changesAndreas Hansson
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
This patch splits the retryList into a list of ports that are waiting for the bus itself to become available, and a map that tracks the ports where forwarding failed due to a peer not accepting the packet. Thus, when a retry reaches the bus, it can be sent to the appropriate port that initiated that transaction. As a consequence of this patch, only ports that are really ready to go will get a retry, thus reducing the amount of redundant failed attempts. This patch also makes it easier to reason about the order of servicing requests as the ports waiting for the bus are now clearly FIFO and much easier to change if desired.
2013-03-26mem: Introduce a variable for the retrying portAndreas Hansson
This patch introduces a variable to keep track of the retrying port instead of relying on it being the front of the retryList. Besides the improvement in readability, this patch is a step towards separating out the two cases where a port is waiting for the bus to be free, and where the forwarding did not succeed and the bus is waiting for a retry to pass on to the original initiator of the transaction. The changes made are currently such that the regressions are not affected. This is ensured by always prioritizing the currently retrying port and putting it back at the front of the retry list.
2013-03-26mem: Add a generic id field to the packet traceAndreas Hansson
This patch adds an optional generic 64-bit identifier field to the packet trace. This can be used to store the sequential number of the instruction that gave rise to the packet, thread id, master id, "sub"-master within a larger module etc. As the field is optional it has a marginal cost if not used.
2013-03-26mem: Add optional request flags to the packet traceAndreas Hansson
This patch adds an optional flags field to the packet trace to encode the request flags that contain information about whether the request is (un)cacheable, instruction fetch, preftech etc.
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
This patch changes the port in the CPU classes to use MasterPort instead of the derived CpuPort. The functions of the CpuPort are now distributed across the relevant subclasses. The port accessor functions (getInstPort and getDataPort) now return a MasterPort instead of a CpuPort. This simplifies creating derivative CPUs that do not use the CpuPort.
2013-03-25x86: Revert [02321b16685f] which breaks m5ops on x86Andreas Sandberg
Changeset 02321b16685f added m5_writefile to m5op_x86.S a second time, which causes a compilation error on when compiling for x86. This changeset reverts that changeset and fixes the error.
2013-03-22config: return exit event instead of causeNilay Vaish
changeset: a4739b6f799d made some changes that where an exit event should have been returned in place of exit cause. This patch corrects the error.
2013-03-22regressions: updates to config.ini for ruby testsNilay Vaish
2013-03-22ruby: slicc: set sender, receiver clock objs for optional queueNilay Vaish
2013-03-22ruby: message buffer: correct previous errorsNilay Vaish
A recent set of patches added support for multiple clock domains to ruby. I had made some errors while writing those patches. The sender was using the receiver side clock while enqueuing a message in the buffer. Those errors became visible while creating (or restoring from) checkpoints. The errors also become visible when a multi eventq scenario occurs.
2013-03-22ruby: message buffer: remove _ptr from some variablesNilay Vaish
The names were getting too long.
2013-03-22ruby: message buffer node: used Tick in place of CyclesNilay Vaish
The message buffer node used to keep time in terms of Cycles. Since the sender and the receiver can have different clock periods, storing node time in cycles requires some conversion. Instead store the time directly in Ticks.
2013-03-22ruby: consumer: avoid using receiver side clockNilay Vaish
A set of patches was recently committed to allow multiple clock domains in ruby. In those patches, I had inadvertently made an incorrect use of the clocks. Suppose object A needs to schedule an event on object B. It was possible that A accesses B's clock to schedule the event. This is not possible in actual system. Hence, changes are being to the Consumer class so as to avoid such happenings. Note that in a multi eventq simulation, this can possibly lead to an incorrect simulation. There are two functions in the Consumer class that are used for scheduling events. The first function takes in the relative delay over the current time as the argument and adds the current time to it for scheduling the event. The second function takes in the absolute time (in ticks) for scheduling the event. The first function is now being moved to protected section of the class so that only objects of the derived classes can use it. All other objects will have to specify absolute time while scheduling an event for some consumer.
2013-03-22ruby: remove unsued profile functionsNilay Vaish
2013-03-22ruby: keep histogram of outstanding requests in seqNilay Vaish
The histogram for tracking outstanding counts per cycle is maintained in the profiler. For a parallel implementation of the memory system, we need that this histogram is maintained locally. Hence it will now be kept in the sequencer itself. The resulting histograms will be merged when the stats are printed.
2013-03-22slicc: remove check if the L1Cache has a sequencerNilay Vaish
2013-03-22ruby: move stall and wakeup functions to AbstractControllerNilay Vaish
These functions are currently implemented in one of the files related to Slicc. Since these are purely C++ functions, they are better suited to be in the base class.
2013-03-22ruby: connect two controllers using only message buffersNilay Vaish
This patch modifies ruby so that two controllers can be connected to each other with only message buffers in between. Before this patch, all the controllers had to be connected to the network for them to communicate with each other. With this patch, one can have protocols where a controller is not connected to the network, but communicates with another controller through a message buffer.
2013-03-22ruby: convert Topology to regular classNilay Vaish
The Topology class in Ruby does not need to inherit from SimObject class. This patch turns it into a regular class. The topology object is now created in the constructor of the Network class. All the parameters for the topology class have been moved to the network class.
2013-03-22ruby: network: move routers from topology to networkNilay Vaish
2013-03-20cpu: Avoid including inorder TLBUnit to avoid gcc LTO bugAndreas Hansson
This patch comments out the inclusion of the inorder TLBUnit which is only used in the 9-stage pipeline. With the TLBUnit present, gcc >= 4.6 in combination with LTO ends up throwing away the definition of the TLBUnit destructor, and consequently fail to link. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53808 for more details about the bug, and http://gcc.gnu.org/ml/gcc/2012-06/msg00397.html for the discussion thread that also touches on similar issues seen with clang.
2013-03-18scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'Andreas Sandberg
tcmalloc_minimal doesn't support the heap checker on Debian, while tcmalloc does. Instead of always linking with tcmalloc_minimal, if it exists, we first check for tcmalloc and then use tcmalloc_minimal as a fallback.
2013-03-18scons: Avoid malloc/free compiler optimization when using tcmallocAndreas Sandberg
According to the tcmalloc readme, the recommended way of compiling applications that make use of tcmalloc is to disable compiler optimizations that make assumptions about malloc and friends. This changeset adds the necessary compiler flags for both gcc and clang. From the tcmalloc readme: "NOTE: When compiling with programs with gcc, that you plan to link with libtcmalloc, it's safest to pass in the flags -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-free when compiling."
2013-03-18scons: Don't explicitly add tcmalloc_minimal to LIBSAndreas Sandberg
SCons automatically adds a library to LIBS if conf.CheckLib succeeds, so there is no need to explicitly add the library.