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AgeCommit message (Expand)Author
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-10style: clean up the Packet stuffNathan Binkert
2008-11-10flags: Provide an object for managing boolean flags for an object.Nathan Binkert
2008-11-10safe_cast: add a new cast function for casts that should always succeed.Nathan Binkert
2008-11-10DmaDevice: fix minor type in error message.Steve Reinhardt
2008-11-10mem: Assert that requests have non-negative size.Steve Reinhardt
2008-11-10Cache: Refactor packet forwarding a bit.Steve Reinhardt
2008-11-09X86: Add x86 reference output for the timing CPU.Gabe Black
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Fix completeAcc get call.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
2008-11-06tracediff: add '#' support for sub-arg alternatives, '-n' paramSteve Reinhardt
2008-11-06Automated merge with ssh://daystrom.m5sim.org//repo/m5Lisa Hsu
2008-11-06Reference updates. Since split cache is gone, a lot of config.ini changes, a...Lisa Hsu
2008-11-05Automated merge with ssh://m5sim.org//repo/m5Lisa Hsu
2008-11-05new mp eio testLisa Hsu
2008-11-05Fix SPARC_FS compileLisa Hsu
2008-11-05Right now a single thread cpu 1 could get assigned context Id != 1, dependingLisa Hsu
2008-11-05Fix a few more places where the context stuff wasn't changedNathan Binkert
2008-11-04decouple eviction from insertion in the cache.Lisa Hsu
2008-11-04Change the findBlock(addr, lat) to accessBlock, which I think has better conn...Lisa Hsu
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-28Libelf: Append options to CCFLAGS for warning free libelf compile instead of ...Ali Saidi
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety o...Clint Smullen
2008-10-27Checkpointing: createCountedDrain function, it was only returning an Event, w...Clint Smullen
2008-10-26BATCH: Run as, ar, and ranlib with BATCH_CMD so that they execute on the batc...Ali Saidi
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-23probe function no longer used anywhere.Lisa Hsu
2008-10-23remove the totally obsolete split cacheLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20Regression: Add single and dual boot O3 regressions. They both take about 8 m...Ali Saidi
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-19Automated merge with ssh://daystrom.m5sim.org//z/repo/m5Lisa Hsu
2008-10-16need to add packet_access.hh in order to get tempalte definitionNathan Binkert
2008-10-16get rid of local variable that's only used in an assert so fast compilesNathan Binkert
2008-10-16Automated merge with ssh://daystrom.m5sim.org//z/repo/m5Lisa Hsu
2008-10-14This function declaration isn't used anywhere.Lisa Hsu
2008-10-14eventq: make python events actually workNathan Binkert
2008-10-14eventq: revert code for unserializing events.Nathan Binkert
2008-10-12CPU: Explain why some code is commented out.Gabe Black
2008-10-12Get rid of some commented out code.Gabe Black
2008-10-12X86: Set the delayed commit flag in x86 microops appropriately.Gabe Black
2008-10-12X86: Make the local APIC timer event generate an interrupt.Gabe Black
2008-10-12X86: Implement the EOI register in the local APIC.Gabe Black
2008-10-12X86: Add some DPRINTFs to the local APIC.Gabe Black
2008-10-12X86: Make auto eoi mode work in the I8259 PIC.Gabe Black