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2011-04-15includes: sort all includesNathan Binkert
2011-04-15style: add sort_includes to the style hookNathan Binkert
2011-04-15style: move style verifiers into classesNathan Binkert
2011-04-15style: add a user interface wrapper classNathan Binkert
makes things work both with mercurial and stand alone with stdio
2011-04-15util: python implementation of a routine that will sort includesNathan Binkert
I didn't realize that the perl version existed when I started this, this version has a lot more features than the previous one since it will sort and separate python, system, and m5 headers in separate groups, it will remove duplicates, it will also convert c headers to stl headers
2011-04-15region: add a utility class for keeping track of regions of some rangeNathan Binkert
This is basically like the range_map stuff in src/base (range already exists in Python). This code is like a set of ranges. I'm using it to keep track of changed lines in source code, but it could be use to keep track of memory ranges and holes in memory regions. It could also be used in memory allocation type stuff. (Though it's not at all optimized.)
2011-04-15SortedDict: add functions for getting ranges of keys, values, itemsNathan Binkert
2011-04-15python: figure out if the m5.internal package exists even with demandimportNathan Binkert
2011-04-13refcnt: Update doxygen commentsNathan Binkert
2011-04-13refcnt: Inline comparison functionsNathan Binkert
2011-04-13main: separate out interact() so it can be used by other functionsNathan Binkert
2011-04-13util: fix the language type functionNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-10ARM: Fix checkpoint restoration in ARM_SE.Ali Saidi
2011-04-10ARM: Get rid of some comments/todos that no longer apply.Ali Saidi
2011-04-06ruby: fixes to support more types of RubyRequestsBrad Beckmann
2011-04-04ARM: Update stats for default inclusion of CF adapter.Ali Saidi
2011-04-04ARM: Include IDE/CF controller by default in PBX model.Ali Saidi
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04Sim: Fix Simulation.py to allow more than 1 core for standard switching.Anthony Gutierrez
This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed.
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
This change uses the locked_mem.hh header to handle implementing CLREX. It simplifies the current implementation greatly.
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode.
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
All the m5op parameters are 64 bits, but we were only sending 32 bits; and the static register indexes were incorrectly specified.
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-04-04ARM: Fix table walk going on while ASID changes errorAli Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
The comment in the code suggests that the checking granularity should be 16 bytes, however in reality the shift by 8 is 256 bytes which seems much larger than required.
2011-04-04IDE: Support x86, Alpha, and ARM use of the IDE controller.Ali Saidi
2011-04-04ARM: Fix checkpointing case where PL111 is powered off.Ali Saidi
2011-04-04ARM: Remove debugging warn that was accidently left in.Ali Saidi
2011-04-04ARM: Fix multiplication error in udelayAli Saidi
2011-04-01hammer: fixed dma uniproc errorBrad Beckmann
Fixed an error reguarding DMA for uninprocessor systems. Basically removed an overly agressive optimization that lead to inconsistent state between the cache and the directory.
2011-03-31CacheMemory: add allocateVoid() that is == allocate() but no return value.Lisa Hsu
This function duplicates the functionality of allocate() exactly, except that it does not return a return value. In protocols where you just want to allocate a block but do not want that block to be your implicitly passed cache_entry, use this function. Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(), and if you do a dummy assignment Entry foo := cache.allocate(address), the C++ compiler will complain of an unused variable. This is kind of a hack to get around those issues, but suggestions welcome.
2011-03-31Ruby: Simplify SLICC and Entry/TBE handling.Lisa Hsu
Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate use of said variables would not be automatically deferenced in SLICC-generated code. Instead, deferences occurred when such variables were passed to functions, and were automatically dereferenced in the bodies of the functions (e.g. the implicitly passed cache_entry). This is a more general way to do it, which leaves in place the assumption that parameters to functions and local variables of type AbstractCacheEntry and TBE are always pointers, but instead of dereferencing to access member variables on a contextual basis, the dereferencing automatically occurs on a type basis at the moment a member is being accessed. So, now, things you can do that you couldn't before include: Entry foo := getCacheEntry(address); cache_entry.DataBlk := foo.DataBlk; or cache_entry.DataBlk := getCacheEntry(address).DataBlk; or even cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
2011-03-31Ruby: Add new object called WireBuffer to mimic a Wire.Lisa Hsu
This is a substitute for MessageBuffers between controllers where you don't want messages to actually go through the Network, because requests/responses can always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered) because you are, after all, going through a network with contention. For systems where you model multiple controllers that are very tightly coupled and do not actually go through a network, it is a pain to have to write a coherence protocol to account for mixed up request/response orderings despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real MessageBuffers when messages do in fact go over a network.
2011-03-31Ruby: have the rubytester pass contextId to Ruby.Lisa Hsu
2011-03-31Ruby: enable multiple sequencers in one controller.Lisa Hsu
2011-03-31Ruby: pass Packet->Req->contextId() to Ruby.Lisa Hsu
It is useful for Ruby to understand from whence request packets came. This has all request packets going into Ruby pass the contextId value, if it exists. This supplants the old libruby proc_id value passed around in all the Messages, so I've also removed the unused unsigned proc_id; member generated by SLICC for all Message types.
2011-03-31Ruby: Bug in SLICC forgot semicolon at end of code.Lisa Hsu
2011-03-29sim: typecast Tick to UTick for eventQ assertKorey Sewell
2011-03-29Power: Fix compilation.Gabe Black
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-28Config: Import math in MI_example.pyNilay Vaish
2011-03-26tests: update reference outputs for ruby cache index changeSteve Reinhardt
MOESI_CMP_token is the only protocol that showed noticeable stats differences.
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
2011-03-25ruby: fixed cache index settingBrad Beckmann