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2005-06-01A few more config updates. Works with regression now.Steve Reinhardt
configs/splash2/run.py: Update file for new config changes. python/m5/config.py: - isParamContext() not defined any more - fix bug with re-assigning vectors over scalars and vice versa --HG-- rename : configs/splash2/run.mpy => configs/splash2/run.py extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-05-29Major cleanup of python config code.Steve Reinhardt
Special mpy importer is gone; everything is just plain Python now (funky, but straight-up). May not completely work yet... generates identical ini files for many configs/kernel settings, but I have yet to run it against regressions. This commit is for my own convenience and won't be pushed until more testing is done. python/m5/__init__.py: Get rid of mpy_importer and param_types. python/m5/config.py: Major cleanup. We now have separate classes and instances for SimObjects. Proxy handling and param conversion significantly reorganized. No explicit instantiation step anymore; we can dump an ini file straight from the original tree. Still needs more/better/truer comments. test/genini.py: Replace LoadMpyFile() with built-in execfile(). Export __main__.m5_build_env. python/m5/objects/AlphaConsole.py: python/m5/objects/AlphaFullCPU.py: python/m5/objects/AlphaTLB.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/CoherenceProtocol.py: python/m5/objects/Device.py: python/m5/objects/DiskImage.py: python/m5/objects/Ethernet.py: python/m5/objects/Ide.py: python/m5/objects/IntrControl.py: python/m5/objects/MemTest.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/Platform.py: python/m5/objects/Process.py: python/m5/objects/Repl.py: python/m5/objects/Root.py: python/m5/objects/SimConsole.py: python/m5/objects/SimpleDisk.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: Fixes for eliminating mpy_importer, and modified handling of frequency/latency params. Also renamed parent to Parent. --HG-- rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-28Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 475f25967577aa47d84b476c07ce0ddfe05078d0
2005-05-28ns_gige_reg.h, ns_gige.cc:Lisa Hsu
clean up code to eliminate license issues. dev/ns_gige.cc: dev/ns_gige_reg.h: clean up code to eliminate license issues. --HG-- extra : convert_revision : 64adbd87faa5ce5ac6b9da4fd95b12796487c8f9
2005-05-26Added copyright.Kevin Lim
--HG-- extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-25Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 13696a8e526f7ded7555d009d03bdc7551557571
2005-05-24Little debugging things.Steve Reinhardt
cpu/base_cpu.cc: Get rid of leftover debugging code. --HG-- extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
2005-05-20Update mem trace reader params.Steve Reinhardt
--HG-- extra : convert_revision : 03807971dacb23801895be45ea1582d2c345c021
2005-05-20Minor changes to get new cpu to compile with FULL_SYSTEM.Steve Reinhardt
cpu/beta_cpu/full_cpu.hh: Make cpu_id protected rather than private so derived classes can access it. cpu/beta_cpu/regfile.hh: Get rid of troublesome debugging statement. --HG-- extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
2005-05-19Fix up code for initial release. The main bug that remains is properly ↵Kevin Lim
forwarding data from stores to loads, specifically when they are of differing sizes. cpu/base_dyn_inst.cc: Remove unused commented out code. cpu/base_dyn_inst.hh: Fix up comments. cpu/beta_cpu/2bit_local_pred.cc: Reorder code to match header file. cpu/beta_cpu/2bit_local_pred.hh: Update comments. cpu/beta_cpu/alpha_dyn_inst.hh: Remove useless comments. cpu/beta_cpu/alpha_dyn_inst_impl.hh: cpu/beta_cpu/alpha_full_cpu_impl.hh: cpu/beta_cpu/comm.hh: cpu/beta_cpu/iew_impl.hh: Remove unused commented code. cpu/beta_cpu/alpha_full_cpu.hh: Remove obsolete comment. cpu/beta_cpu/alpha_impl.hh: cpu/beta_cpu/full_cpu.hh: Alphabetize includes. cpu/beta_cpu/bpred_unit.hh: Remove unused global history code. cpu/beta_cpu/btb.hh: cpu/beta_cpu/free_list.hh: Use full path in #defines. cpu/beta_cpu/commit.hh: cpu/beta_cpu/decode.hh: Reorder functions. cpu/beta_cpu/commit_impl.hh: Remove obsolete commented code. cpu/beta_cpu/fetch.hh: Remove obsolete comments. cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/rename_impl.hh: Remove commented code. cpu/beta_cpu/full_cpu.cc: Remove useless defines. cpu/beta_cpu/inst_queue.hh: Use full path for #defines. cpu/beta_cpu/inst_queue_impl.hh: Reorder functions to match header file. cpu/beta_cpu/mem_dep_unit.hh: Use full path name for #defines. cpu/beta_cpu/ras.hh: Use full path names for #defines. Remove mod operation. cpu/beta_cpu/regfile.hh: Remove unused commented code, fix up current comments. cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Update programming style. --HG-- extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
2005-05-17Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5Kevin Lim
--HG-- extra : convert_revision : c403960153ed648e7da7251465ca9350ba10cd27
2005-05-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 5437b6fde4c09b8890d2bfa0cfba3d7e509a0f92
2005-05-15Fix "no supplier" bug.Steve Reinhardt
--HG-- extra : convert_revision : 01549db31d2094c58c6875fbbf79d4e07e7e39f9
2005-05-14More cleanup of fetch code.Steve Reinhardt
--HG-- extra : convert_revision : a2279283be76341467e228ad1d56989a2be383eb
2005-05-13Add mem_trace parameter to BaseCache.Steve Reinhardt
python/m5/objects/BaseCache.mpy: Add mem_trace parameter. --HG-- extra : convert_revision : a0bab53fabd7426eee5ca9c845c02a6ac2e1722f
2005-05-13panic vs fatal fixes in bus.ccSteve Reinhardt
base/misc.hh: Add some comments explaining the difference between panic() and fatal(). --HG-- extra : convert_revision : 876f0c98276fa1060c0589dc179022a297a8ed2e
2005-05-12Force pipeline drain on first instruction of async interrupt handler.Steve Reinhardt
Done by marking DynInst as serializing... requires adding the ability to check both DynInst and StaticInst for serializing behavior. --HG-- extra : convert_revision : 00db3e16d3b13dd9663f5a9f1bd8f724ed499914
2005-05-12Get rid of unused SMT code from FullCPU.Steve Reinhardt
--HG-- extra : convert_revision : 7a047b36718a44a8f3a43e3c0f54ca796d19f10a
2005-05-09Add definitions for memory trace writers.Steve Reinhardt
--HG-- extra : convert_revision : bb27c2a2ba8f97f186b712165db9a25f3fe61dda
2005-05-04Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5Kevin Lim
--HG-- extra : convert_revision : b868e7920eaa3682c6123651f0c598673ebb7f22
2005-05-03Add support for dedicated 1GHz Simple CPURon Dreslinski
New examples of test.py files in ~rdreslin/jobs/ancs0 and ~rdreslin/cpt/ancs0 --HG-- extra : convert_revision : c2337874199fae9cbd43da9dbc3b9bd85ea2c92e
2005-05-03Large update of several parts of my code. The most notable change is the ↵Kevin Lim
inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-02Fix ethernet configurationNathan Binkert
--HG-- extra : convert_revision : 9ee6e620b722d39d234b15785852a6cc00ffe041
2005-05-02Skip calibrate delay again.Nathan Binkert
kern/linux/linux_system.cc: calibrate delay starts three instructions after the symbol now. --HG-- extra : convert_revision : f9c2bed3bca1f3394801fe7696cfff870443c204
2005-05-02Make sinic work with mpyNathan Binkert
dev/sinic.cc: dev/sinic.hh: Fix sinic parameters. (header_bus -> io_bus) python/m5/objects/Ethernet.mpy: Add simobj definitions for sinic. --HG-- extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
2005-05-02workaround configuration bug in tick is ps.Nathan Binkert
--HG-- extra : convert_revision : 301b6e4d590efc7a4d11959a932d5349edc59041
2005-05-02Improve checkpointing of ethernet packets a bit.Nathan Binkert
dev/etherpkt.cc: Don't try to suck in the packet if the length is zero. --HG-- extra : convert_revision : 7212f3b677777fbce301f0613b9f513bb9fe057e
2005-05-02Better configurations for checkpointing. Add more NIC options.Nathan Binkert
--HG-- extra : convert_revision : d0b9ccbcb4ac14f0d305bfcbfb9a041dfb5d3465
2005-05-02Make sure to just do the dma No Allocation on readsRon Dreslinski
--HG-- extra : convert_revision : f5d0b6753958c36fd3678c61b5e9af943e24d517
2005-05-02Add environment parameter for Allocation policy of DMA'sRon Dreslinski
--HG-- extra : convert_revision : 444952065b0508c083e8c64fa5f9f5a761787900
2005-05-02Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-04-30Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/clean --HG-- extra : convert_revision : eb92d2799c76fad09f6b5a9476e4e9fc7c8dbfca
2005-04-30Handle no_allocates as needing the response in miss_queue, like uncacheablesRon Dreslinski
Add support for hit under miss of a no allocate (It seems as though DMA reads to the same block happen close together, is this an artifact of the header/payload splitting) Make sure to respond to all targets of a no_allocate request --HG-- extra : convert_revision : a9d733f499face4039929524573ffc9500e93d83
2005-04-30Cleanup rcS files. Make sure there are enough tracked connections.Nathan Binkert
Delay before singalling peer to make sure that the peer is ready configs/boot/nat-netperf-server.rcS: delay before singalling to make sure that the natbox is ready configs/boot/nat-netperf-stream-client.rcS: increase the number of tracked connections configs/boot/nat-spec-surge-client.rcS: configs/boot/nfs-client-nhfsstone.rcS: configs/boot/nfs-client-smallb.rcS: configs/boot/nfs-client-tcp-smallb.rcS: configs/boot/nfs-client-tcp.rcS: configs/boot/nfs-client.rcS: configs/boot/nfs-server.rcS: configs/boot/spec-surge-client.rcS: configs/boot/spec-surge-server.rcS: configs/boot/surge-client.rcS: configs/boot/surge-server.rcS: increase the number of tracked connections cleanup configs/boot/nat-spec-surge-server.rcS: configs/boot/natbox-netperf.rcS: configs/boot/nfs-server-nhfsstone.rcS: delay before singalling to make sure that the natbox is ready increase the number of tracked connections cleanup configs/boot/natbox-spec-surge.rcS: delay before singalling to make sure that the natbox is ready increase the number of tracked connections --HG-- extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
2005-04-29Add suport for no allocation of cache block on a dma read passing through a ↵Ron Dreslinski
cache from the cpu-side interface --HG-- extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
2005-04-28Clean up output for pc break events, and remove a unneeded break event.Ron Dreslinski
cpu/pc_event.cc: Add a newline to the printout to clean up output kern/linux/linux_system.cc: Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts --HG-- extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-28Make ip_conntrack table size largerRon Dreslinski
--HG-- extra : convert_revision : bda54b29cb15144907b186f06517477dea13ba06
2005-04-24Add the m5 parameter to the ns83820 device model so that weNathan Binkert
can pass simulator specific options to the device driver. dev/ns_gige.cc: Add the m5 register and parameter to the ns83820 device model so that we can pass simulator specific options to the device driver. dev/ns_gige.hh: dev/ns_gige_reg.h: Add the m5 register to the ns83820 device model --HG-- extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
2005-04-24cleanup mpy fileNathan Binkert
--HG-- extra : convert_revision : ddde8f1b60dfa0c637d82d9217e713f071af6ccb
2005-04-22Make code more portable and port to cygwinNathan Binkert
arch/alpha/alpha_tru64_process.cc: getdirent isn't implemented by cygwin. panic if this function is executed. (It shouldn't be too much to emulate it using opendir, readdir, etc.) arch/alpha/pseudo_inst.cc: Use lseek once and read instead pread. base/intmath.hh: we want int, long, and long long variations of FloorLog2 instead of int32_t, int64_t. Otherwise, we leave one out. base/socket.cc: Fix define that seems to be for apple sim/serialize.cc: don't use the intXX_t stuff, instead, use the real types so we're sure that we cover all of them. --HG-- extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
2005-04-17Mostly hacks for multiplying Frequency-type proxies by constantsSteve Reinhardt
(plus some small fixes). python/m5/config.py: Hacks to allow multiplication on Frequency/Latency-valued proxies. Provide __rmul__ as well as __mul__ on Proxy objects. test/genini.py: Default value for -EFOO should be True not 1 (since 1 is no longer convertable to Bool). --HG-- extra : convert_revision : f8a221fcd9e095fdd7b7db4be0ed0cdcd20074be
2005-04-15Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : febc87fb6083ef8b80a2bc91a766ea9e13d82744
2005-04-14FRon Dreslinski
--HG-- extra : convert_revision : 22245997131432986d94105957461275ee4ae07e
2005-04-14Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-13Make multiple calls to SimExit work.Nathan Binkert
--HG-- extra : convert_revision : 91a5652913b7278efe6a3a4955e5e2f723ba59eb
2005-04-13Make the exit after max checkpoints code compile.Nathan Binkert
sim/serialize.cc: call exitNow instead of SimExit. Include the header too. --HG-- extra : convert_revision : 633a8533b23cac914a2b09bd2d3ea5d85243c675
2005-04-13Add support to limit the number of checkpoints dropped.Nathan Binkert
sim/serialize.hh: Add variables to keep track of the number of checkpoints dropped and maximum allowed. --HG-- extra : convert_revision : 32241b90c58def6958ec84c53cc2cca996007506
2005-04-11Fixup split stats.Nathan Binkert
--HG-- extra : convert_revision : 5f3d162c3f4d90f481393f812e6138c659e4f6e2
2005-04-11Update for changes in the way latencies and bandwidths are dealt with.Nathan Binkert
--HG-- extra : convert_revision : 1d183bf47222599ee11154ab0c9eb9cd99a29806
2005-04-11Make the notion of a global event tick independent of the actualNathan Binkert
CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-19 13:34:17 +0000