gem5 - gem5

Age	Commit message (Expand)	Author
2016-12-05	mem: Invalidate a blk when servicing the 1st invalidating target	Nikos Nikoleris
2016-12-05	mem: Allow non invalidating snoops on an InvalidateReq MSHR	Nikos Nikoleris
2016-12-05	mem: Don't use hasSharers in the snoopFilter for memory responses	Nikos Nikoleris
2016-12-05	mem: Always use InvalidateReq to service WriteLineReq misses	Nikos Nikoleris
2016-12-05	mem: Assert that the responderHadWritable is set only once	Nikos Nikoleris
2016-12-05	mem: Ensure InvalidateReq is considered isForward by MSHRs	Andreas Hansson
2016-12-05	mem: Make packet debug printing more uniform	Nikos Nikoleris
2016-12-05	cpu: Change traffic generators to use different values for writes	Nikos Nikoleris
2016-12-05	mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv	Nikos Nikoleris
2016-12-05	mem: Keep track of allocOnFill in the TargetList	Nikos Nikoleris
2016-12-05	mem: Add support for repopulating the flags of an MSHR TargetList	Nikos Nikoleris
2016-12-02	hsail: disable asserts to allow immediate operands i.e. 0 with loads	Brandon Potter
2016-12-02	hsail: add stub type and stub out several instructions	Brandon Potter
2016-12-02	hsail: add popcount type and generate popcount instructions	Brandon Potter
2016-12-02	hsail: add a wavesize case statement to register operand code	Brandon Potter
2016-12-02	hsail: generate mov instructions for more arith_types and bit_types	Brandon Potter
2016-12-02	hsail: remove the panic guarding function directives	Brandon Potter
2016-12-02	hsail: fix unsigned offset bug in address calculation	Tony Gutierrez
2016-12-02	ruby: Fix overflow reported by ASAN in MessageBuffer.	Matthew Poremba
2016-11-30	tests: Regression stats updated for recent patches	Jason Lowe-Power
2016-11-30	riscv: [Patch 8/5] Added some regression tests to RISC-V	Alec Roelke
2016-11-30	riscv: [Patch 7/5] Corrected LRSC semantics	Alec Roelke
2016-11-30	riscv: [Patch 6/5] Improve Linux emulation for RISC-V	Alec Roelke
2016-11-30	riscv: [Patch 5/5] Added missing support for timing CPU models	Alec Roelke
2016-11-30	riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A	Alec Roelke
2016-11-30	riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD	Alec Roelke
2016-11-30	riscv: [Patch 2/5] Added RISC-V multiply extension RV64M	Alec Roelke
2016-11-30	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	Alec Roelke
2016-11-30	mem: Split the hit_latency into tag_latency and data_latency	Sophiane Senni
2016-11-30	cpu: Remove branch predictor function predictInOrder	Jason Lowe-Power
2016-11-30	tests: Check for TrafficGen as part of memcheck regression	Andreas Hansson
2016-11-29	dev: Fix buffer length when unserializing an eth pkt	Michael LeBeane
2016-11-28	scons: fix sanitizer flags with multiple sanitizers	Joe Gross
2016-11-25	style: Add options to select checkers and apply fixes	Andreas Sandberg
2016-11-25	util: git pre-commit hook to check staged files	Rekai Gonzalez Alberquilla
2016-11-21	ruby: Fix potential bugs in garnet2.0	Jieming Yin
2016-11-21	gpu-compute: fix segfault when constructing GPUExecContext	Tony Gutierrez
2016-11-21	gpu-compute: init valid field of GpuTlbEntry in default ctor	Tony Gutierrez
2016-11-21	ruby: add default ctor for MachineID type	Tony Gutierrez
2016-11-21	x86: fix issue with casting in Cvtf2i	Tony Gutierrez
2016-11-19	ruby: init MessageSizeType of SequencerMsg to Request_Control	Sooraj Puthoor
2016-11-19	x86: fix loading/storing of Float80 types	Tony Gutierrez
2016-11-18	ext: Update fputils to rev 13589cd	Andreas Sandberg
2016-11-17	stats, alpha: Update ALPHA stats	Andreas Hansson
2016-11-17	tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)	Andreas Hansson
2016-11-17	alpha: Remove ALPHA tru64 support and associated tests	Andreas Hansson
2016-10-26	hsail,gpu-compute: fixes to appease clang++	Tony Gutierrez
2016-10-26	dev: Add m5 op to toggle synchronization for dist-gem5.	Michael LeBeane
2016-10-26	ruby: Allow multiple outstanding DMA requests	Michael LeBeane
2016-10-26	dev: Add 'simLength' parameter in EthPacketData	mlebeane