summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2006-05-16Add some flags for the upcoming checker.Kevin Lim
arch/alpha/isa/decoder.isa: Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty. Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct. cpu/static_inst.hh: Add unverifiable flag, specifically for the CheckerCPU. --HG-- extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
2006-05-11Fixes for ozone CPU to successfully boot and run linux.Kevin Lim
cpu/base_dyn_inst.hh: Remove snoop function (did not mean to commit it). cpu/ozone/back_end_impl.hh: Set instruction as having its result ready, not completed. cpu/ozone/cpu.hh: Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost). Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps. Also support the new Checker. cpu/ozone/cpu_builder.cc: Add parameter for maxOutstandingMemOps so it can be set through the config. Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future. cpu/ozone/cpu_impl.hh: Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast. Support switching out/taking over from other CPUs. Correct indexing problem for float registers. cpu/ozone/dyn_inst.hh: Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers. cpu/ozone/dyn_inst_impl.hh: Support waiting on memory operations. Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed. cpu/ozone/front_end.hh: Support switching out. Also record if an interrupt is pending. cpu/ozone/front_end_impl.hh: Support switching out. Also support stalling the front end if an interrupt is pending. cpu/ozone/lw_back_end.hh: Add checker in. Support switching out. Support memory barriers. cpu/ozone/lw_back_end_impl.hh: Lots of changes to get things to work right. Faults, traps, interrupts all wait until all stores have written back (important). Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions. cpu/ozone/lw_lsq.hh: Support switching out. Also use store writeback events in all cases, not just dcache misses. cpu/ozone/lw_lsq_impl.hh: Support switching out. Also use store writeback events in all cases, not just dcache misses. Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results). cpu/ozone/simple_params.hh: Add max outstanding mem ops parameter. python/m5/objects/OzoneCPU.py: Add max outstanding mem ops, checker. --HG-- extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-11Small fixes to O3 model.Kevin Lim
cpu/o3/alpha_dyn_inst.hh: Set the instResult using a function on the base dyn inst. cpu/o3/bpred_unit_impl.hh: Don't need to reset the state. cpu/o3/commit_impl.hh: Mark instructions as completed. Wait until all stores are written back to handle a fault. cpu/o3/cpu.cc: Clear instruction lists when switching out. cpu/o3/lsq_unit.hh: Allow wbEvent to be set externally. cpu/o3/lsq_unit_impl.hh: Mark instructions as completed properly. Also use events for writing back stores even if there is a hit in the dcache. --HG-- extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c
2006-05-11Set memory properly.Kevin Lim
--HG-- extra : convert_revision : 4e6c61d31bf052bb4aabf4bb7a4f0e870b44b771
2006-05-11Separate out result being ready and the instruction being complete.Kevin Lim
--HG-- extra : convert_revision : 9f17af114bf639f8fb61896e49fa714932c081d7
2006-05-04O3 CPU now handles being used with the sampler.Kevin Lim
cpu/o3/2bit_local_pred.cc: cpu/o3/2bit_local_pred.hh: cpu/o3/bpred_unit.hh: cpu/o3/bpred_unit_impl.hh: cpu/o3/btb.cc: cpu/o3/btb.hh: cpu/o3/commit.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/decode.hh: cpu/o3/decode_impl.hh: cpu/o3/fetch.hh: cpu/o3/fetch_impl.hh: cpu/o3/fu_pool.cc: cpu/o3/fu_pool.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: cpu/o3/lsq.hh: cpu/o3/lsq_impl.hh: cpu/o3/lsq_unit.hh: cpu/o3/lsq_unit_impl.hh: cpu/o3/mem_dep_unit.hh: cpu/o3/mem_dep_unit_impl.hh: cpu/o3/ras.cc: cpu/o3/ras.hh: cpu/o3/rename.hh: cpu/o3/rename_impl.hh: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/o3/thread_state.hh: Handle switching out and taking over. Needs to be able to reset all state. cpu/o3/alpha_cpu_impl.hh: Handle taking over from another XC. --HG-- extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449
2006-05-03Fixes for the sampler.Kevin Lim
cpu/simple/cpu.cc: Sampler fixes. The status may be switched out when calling activate or suspend if there is a switchover during a quiesce. --HG-- extra : convert_revision : da026e75dfb86289484cf01c5b1ecd9b03a72bd3
2006-05-03XC needs to get memory from the process.Kevin Lim
--HG-- extra : convert_revision : a2c014276824255a896a7e353f919fe81071091e
2006-04-24Quiesce stuff.Kevin Lim
cpu/ozone/cpu.hh: Add quiesce stat (not clear how it should be used yet). cpu/ozone/cpu_impl.hh: Fix for quiesce. --HG-- extra : convert_revision : a1998818e241374ae3f4c3cabbef885dda55c884
2006-04-24Include option for disabling PC symbols.Kevin Lim
cpu/inst_seq.hh: cpu/o3/cpu.cc: cpu/ozone/cpu_builder.cc: cpu/ozone/thread_state.hh: SE build fixes. --HG-- extra : convert_revision : a4df6128533105f849b5469f62d83dffe299b7df
2006-04-24Updates to Ozone model for quiesce, store conditionals.Kevin Lim
--HG-- extra : convert_revision : 72ddd75ad0b5783aca9484e7d178c2915ee8e355
2006-04-24New stats added to O3 model.Kevin Lim
--HG-- extra : convert_revision : 7abb491e89e3e1a331cd19aa05ddce5184abf9e0
2006-04-24Fixes for ll/sc for the O3 model.Kevin Lim
cpu/o3/alpha_cpu.hh: Store conditionals should not write their data to memory if they failed. cpu/o3/lsq_unit.hh: Setup request parameters when they're needed. --HG-- extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
2006-04-24Allow the switching on and off of PC symbols for tracing.Kevin Lim
--HG-- extra : convert_revision : a2422e30ace9874ba1be44cd0e1d3024cabbf1ed
2006-04-24Use dwarf-2 debugging symbols (they work much better).Kevin Lim
--HG-- extra : convert_revision : 669e4c32f2bc2c035a4199d6152a638b75a25148
2006-04-22Include new OzoneCPU filesKevin Lim
--HG-- extra : convert_revision : f8c8751aab62df5d57c6491c5ce9b90b5a176e86
2006-04-22Updates for OzoneCPU.Kevin Lim
cpu/static_inst.hh: Updates for new CPU, also include a classification of quiesce instructions. --HG-- extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
2006-04-22Remove unnecessary functions.Kevin Lim
cpu/exec_context.hh: Remove functions that shouldn't be accessible to anything outside of the CPU. --HG-- extra : convert_revision : 9793c3ceb6d5404484bafc7a75d75ed71815d9eb
2006-04-22Update the python file for the CPU.Kevin Lim
--HG-- extra : convert_revision : be899403d893f5ab6c11ae5a4334c0e36bd6ff61
2006-04-22Updates for OzoneCPU.Kevin Lim
build/SConstruct: Include Ozone CPU models. cpu/cpu_models.py: Include OzoneCPU models. --HG-- extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
2006-04-22Updates for O3 model.Kevin Lim
arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-22Namespace fix.Kevin Lim
base/timebuf.hh: namespace fix. --HG-- extra : convert_revision : 38e880b9394cf2923e2fb9775368cd93d719f950
2006-04-22Move quiesce event to its own class.Kevin Lim
SConscript: Move quiesce event to its own file/class. --HG-- extra : convert_revision : 6aa7863adb529fc03142666213c3ec348825bd3b
2006-04-22Move TLB faults into the normal fault classes. Now they are executed when ↵Kevin Lim
the fault is invoked. --HG-- extra : convert_revision : b5f00fff277e863b3fe43422bc39d0487c482e60
2006-03-29Fix indentationRon Dreslinski
--HG-- extra : convert_revision : 321ff3c6e8dcc41f18e983fac83e14c037081dcb
2006-03-29Fix for prefetching check with blocking buffers. Need to look into support ↵Ron Dreslinski
for prefetching with blocking buffers. --HG-- extra : convert_revision : 7b401cf76742ffda6c911faf710970c58a0c337b
2006-03-29Add some basic statistics to the disk modelRon Dreslinski
--HG-- extra : convert_revision : 0f3a45745b0122de64a2f434604a474df04f2938
2006-03-28Make the .mpy file a .py file and convert it to the form recognized now.Ron Dreslinski
--HG-- extra : convert_revision : 1019fd1e2bb484e1ea8f15db8dbe8e7a0201bd58
2006-03-27Add the detailed DRAM model into M5. See the /mem/timing/DRAM_M5.txt for ↵Ron Dreslinski
discussion on setting paramaters. SConscript: Add support for detailed DRAM model --HG-- extra : convert_revision : b65f9a810fa95957b585c85632ac20f9283337d1
2006-03-23Add support in the fullsys script to run the POVray benchmark.Ron Dreslinski
To run it use -ETEST=POVRAY_BENCH to run the built in povray benchmark program (more CPU intensive, small fileset ~11MB) -ETEST=POVRAY_AUTUMN to run the first part of a rendering of a autumn leaves/tree scene, less cpu intensive ~500MB working set. For now I have been running with -ESYSTEM=Simple in order to drop checkpoints (built into binary at the point the render begins) and create memory traces. I will check in a SYSTEM=3D_DRAM and SYSTEM=3D_CACHE configuration as soon as those are ready. --HG-- extra : convert_revision : fb55834a02317d5e9961a5145c932965c8bc6a0e
2006-03-16Don't forget to check in the needed header file for the conditional prefetch ↵Ron Dreslinski
building. --HG-- extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
2006-03-15Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5 --HG-- extra : convert_revision : a4de274ec50821218121ba38f9215f2348262c27
2006-03-15Add support for conditional compiling in of prefetchers.Ron Dreslinski
--HG-- extra : convert_revision : 357554632f102224357c8c3848bc4bc7cbb9dc54
2006-03-15Don't access init_regs directly. This does not affect newmem; Steve already ↵Kevin Lim
changed this in newmem. --HG-- extra : convert_revision : 19b1ed0bb2c8bcde72843e62f73635e84adf95b5
2006-03-14Remove unneeded header files.Ron Dreslinski
Add some forward declerations. Fix ordering problem of variables in constructor (see sourceforge) Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size) --HG-- extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
2006-03-12Get rid of obsolete header that had only one declaration ofSteve Reinhardt
an obsolete function that doesn't exist. arch/alpha/tru64/process.cc: sim/process.cc: Don't include useless header. --HG-- extra : convert_revision : 1dd5edeb0703e2190b89ea5ff563df4c95b7cf59
2006-03-10Wrapped setSysCallReturn in !FULL_SYSTEM.Gabe Black
--HG-- extra : convert_revision : c6d3a5af04731a92eaca2337424ba10926f0d879
2006-03-09fix merging issuesAli Saidi
arch/alpha/isa_traits.hh: arch/sparc/linux/process.cc: fix merging problem sim/syscall_emul.cc: use setIntReg --HG-- extra : convert_revision : e88d72e415493cd17d7b88c22c7e995f3199e396
2006-03-09Merge zizzer:/bk/multiarchAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.ma2 arch/alpha/isa_traits.hh: arch/alpha/linux/process.cc: arch/sparc/isa_traits.hh: arch/sparc/linux/process.cc: sim/process.cc: merge --HG-- rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : fea0155c8e23abbd0d5d5251abbd0f4d223fe935
2006-03-09no more common syscall emulation, now common for everyoneAli Saidi
check abi-tag note section of elf binary for OS add pseudo functions (moved from alpha and made to be generic) move setsyscallreturn into isa traits arch/alpha/SConscript: no more common syscall emulation, now common for everyone arch/alpha/isa_traits.hh: move setsyscallreturn into isa description arch/alpha/linux/process.cc: arch/alpha/tru64/process.cc: use generic functions rather than alpha specific ones arch/sparc/isa_traits.hh: have consts for generic pseudo syscalls arch/sparc/linux/process.cc: use generic functions base/loader/elf_object.cc: check abi-tag note section of elf binary for OS cpu/exec_context.hh: move syssyscallreturn into isa traits sim/process.cc: find call num with a more generic sim/syscall_emul.cc: sim/syscall_emul.hh: add pseudo functions (moved from alpha and made to be generic) --HG-- extra : convert_revision : 5a31024ecde7e39b830365ddd84593ea501a34d2
2006-03-09Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Gabe Black
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch cpu/simple/cpu.cc: Hand Merge --HG-- rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
2006-03-09Use functions to access XC.Kevin Lim
cpu/exec_context.hh: Include readNextNPC function. cpu/simple/cpu.cc: Use functions to set and access nextPC, nextNPC. --HG-- extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
2006-03-09last changes before big mergeKorey Sewell
arch/alpha/isa_traits.hh: arch/sparc/isa_traits.hh: add nnpc for compiling purposes in exec_context setNextNPC function cpu/exec_context.hh: set NNPC function cpu/simple/cpu.cc: use NNPC in determining what PC we are using --HG-- extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
2006-03-09minor comments to decoder.isaKorey Sewell
arch/mips/isa/decoder.isa: comments --HG-- extra : convert_revision : 8e4fdf36d7f7365cda062bc169a313bf860a4fe5
2006-03-08Merge zizzer:/bk/multiarchKorey Sewell
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch-m5 --HG-- extra : convert_revision : f3502f293f6ea44b5cf209ce2a935a25bca6054f
2006-03-08add explicit support for nop,ssnop, and ehb instructionsKorey Sewell
--HG-- extra : convert_revision : 41151d38cabb6ce0ea81e5d78e4474d8f2ffeb67
2006-03-08Include ability to copy all misc regs.Kevin Lim
arch/alpha/ev5.cc: Include function for the MiscRegFile to copy all of the Iprs from an ExecContext. arch/alpha/isa_traits.hh: Include functions to copy MiscRegs from an ExecContext. cpu/cpu_exec_context.cc: Be sure to copy all of the misc regs when copying all architectural state. --HG-- extra : convert_revision : cb948b5ff141ea0f739a1016f98236bd2a512f76
2006-03-08Merge ktlim@zizzer:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc arch/alpha/ev5.cc: cpu/o3/cpu.hh: SCCS merged --HG-- extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166
2006-03-08Forward declaration of MemoryController.Kevin Lim
My change to exec_context.hh probably affected these files to no longer have MemoryController forward declared through a long chain of includes. MemoryController should be forward declared where it is used anyways. dev/alpha_console.hh: dev/uart.hh: dev/uart8250.hh: Forward declaration of MemoryController. --HG-- extra : convert_revision : afaac4014e0eb3b6d5d385cd4444b77511e03b51
2006-03-08Merge gblack@m5.eecs.umich.edu:/bk/multiarchGabe Black
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 5fe5a3d70774d6420b890237d9be4a5d0f00d17e
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 07:35:12 +0000