Age | Commit message (Collapse) | Author |
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or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3"
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extra : convert_revision : f4f1d3fd0fb28468b0ee507aaadf3c14aa9cf924
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
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extra : convert_revision : 7e8c3572ede7d93910fc3e2a2e76d9a38b1f4243
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
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src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
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extra : convert_revision : 139b3f480ee6342b37b5642e072c8486d91a3944
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
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extra : convert_revision : e0eb0240848698496bd55093a313eb2e0f512ebc
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into pb15.local:/Users/ali/work/m5.newmem
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extra : convert_revision : 887b278dac6db5ea17ade641de84d0ab8b05db96
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into pb15.local:/Users/ali/work/m5.newmem
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extra : convert_revision : e0057583132ce545eb1867b446484e8984b97282
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relevant code directly into the SimConsole object. Now,
you can easily turn off the listen port by just specifying
0 as the port.
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extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
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extra : convert_revision : ce7ac94da0ed6bad457a8a9e4c949b0c3b09c2ae
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initialized.
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
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util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
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rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
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This basically involves moving the builder code outside of any
namespace. While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.
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extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
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specified.
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extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
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extra : convert_revision : bab45577db1967de1dd88ec9b228f106a4ab7479
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based on the swig modules that we have
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extra : convert_revision : 2fd12db39d46608a62b9df36c2b36189f1d2bc30
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this is just a shuffling around of code and fixes to make
stuff commit properly
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extra : convert_revision : fda9ab0d04f77f27810018a8639d6ea8abb59326
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
"Hand merge" that just used the local file.
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extra : convert_revision : 24c7fa192094958be5a9d17c3461f3328079fd3b
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extra : convert_revision : 135274a64ead4962faa4f34b2df4e9de453cbe7f
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because simple-atomic doesn't seem affected.
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extra : convert_revision : 6a8c77f0ca76eb06ac7eb5216af6adba3759c4c7
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 10d4dc08411c7a433a7194e94f69ca1d639a1ce7
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src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
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extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
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relevant stuff has now been moved to python.
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extra : convert_revision : 608e5ffd0e2b33949a2b183117216f136cfa4484
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since they're no longer used
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extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
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FullCPU
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extra : convert_revision : d7fc876333fc3474bc3827f710aa472e2ad847f4
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expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
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extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
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to loop through it. This is more important as we get rid
of param contexts
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extra : convert_revision : 5a24048b5c3d609285da83dfcb106910afad6919
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extra : convert_revision : 6357ade64deb42fae68b2766545b1c4cdc673fc9
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on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.
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extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
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back into python so we don't just silently ignore those errors
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extra : convert_revision : e2f5566a4681f1b8ea80af50071119118afa7d8a
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extra : convert_revision : 6249d3697c74a0f9f9b2f03857b75785b02bfc8b
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extra : convert_revision : 613eeaf5b3ba5d504e1208f907312a22fe02c0c7
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : f9fd4df544144a691bb5956e3f84036a61822547
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extra : convert_revision : 5edf0ad492fe438d66bcf0ae469ef841cd71e157
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : 4878ca509f9982c065933a41ffc87808edb08b00
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src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
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extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
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extra : convert_revision : 1a20ef41684564e12555e2ff353f19b8a6275406
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for store conditional.
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extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
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extra : convert_revision : 9ecfd5a0a151c03503e42faf98240da12fd719b1
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the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.
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extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
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