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AgeCommit message (Expand)Author
2007-08-10Regression: Add an I/O Cache to the full system regressions that have a cache.Ali Saidi
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-10Bus: Only call end() on an stl object once in a loopAli Saidi
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-07Alpha: Fix an off by one error with the tlb caching mechanism.Gabe Black
2007-08-07Merge with head.Gabe Black
2007-08-07Statetrace: Make statetrace do string instructions all at once like m5 does.Gabe Black
2007-08-07X86: Added some missing parenthesis in the condition code calculation function.Gabe Black
2007-08-07X86: Implemented and hooked in SCAS (scan string)Gabe Black
2007-08-07X86: Add a format to handle string instructions which can use the repe and re...Gabe Black
2007-08-07X86: Overhaul of ruflags to get it to work correctly.Gabe Black
2007-08-07X86: Make a microcode branch microop.Gabe Black
2007-08-04Merge with head.Gabe Black
2007-08-04X86: Implement microops and instructions that manipulate the flags register.Gabe Black
2007-08-04X86: Make 64 bit unaligned accesses work as well as the other sizes.Gabe Black
2007-08-04X86: Make the open flags correct.Gabe Black
2007-08-04X86: Make fixed register operands ignore register index extensions from the R...Gabe Black
2007-08-04X86: Implement the cmpxchg instruction.Gabe Black
2007-08-04X86: Start implementing segmentation support.Gabe Black
2007-08-04X86: Create a base enum value for indexing into a region of the miscregs.Gabe Black
2007-08-04X86: Add the arch_prctl system call and fix up some microcoding.Gabe Black
2007-08-04switching: turn on profiling after a switch if there's an eventNathan Binkert
2007-08-04switching: Remove the drain and resume code from the switching code.Nathan Binkert
2007-08-04python: use the enum values in the memory mode changing codeNathan Binkert
2007-08-04swig: %include all of the enums to get all of the definitions.Nathan Binkert
2007-08-04mergeNathan Binkert
2007-08-04python: provide access to statsNathan Binkert
2007-08-04main: return an an exit code of 1 when we exit due to a python exception.Nathan Binkert
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-08-04port: Implement cache for port interfaces and rangesVincentius Robby
2007-08-04alpha: Implement a cache for recently used page table entriesVincentius Robby
2007-08-04StaticInst: Fix decode cache initialization. Cache functionality was negated.Vincentius Robby
2007-08-03Add cscope files to .hgignore.Steve Reinhardt
2007-08-03tests: new ref outputs for new cache modelSteve Reinhardt
2007-08-03tests: replace all dest ref files on upgrade (if possible).Steve Reinhardt
2007-08-03tests: config.out no longer exists, eliminate ref copy.Steve Reinhardt
2007-08-03merge from headSteve Reinhardt
2007-08-03cache: get rid of obsolete params from python.Steve Reinhardt
2007-08-02Merge with head.Gabe Black
2007-08-02python: Improve support for python calling back to C++ member functions.Nathan Binkert
2007-08-02Merge: No changesAli Saidi
2007-08-02Serialize: This shouldn't have been commited, I got a little bit carried away...Ali Saidi
2007-08-02X86: Get rid of some debug warnings.Gabe Black
2007-08-02Merge with head.Gabe Black
2007-08-02X86: Finally get the x86 initial stack frame right.Gabe Black
2007-08-02X86: Fix special case with SIB index register and REX prefix.Gabe Black
2007-08-02merge: no manual changesNathan Binkert
2007-08-02python: fix m5.build_env variable.Nathan Binkert
2007-08-02merge, no manual changesAli Saidi
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