Age | Commit message (Expand) | Author |
2014-06-30 | arm: make the bi-mode predictor the default for O3_ARM_v7a_BP | Anthony Gutierrez |
2014-06-22 | stats: update for O3 changes | Steve Reinhardt |
2014-06-21 | x86: fix table walker assertion | Binh Pham |
2014-06-21 | o3: make dispatch LSQ full check more selective | Binh Pham |
2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
2014-06-10 | scons: Bump the compiler version to gcc 4.6 and clang 3.0 | Andreas Hansson |
2014-06-09 | Util: Do not style check symlinks | Joel Hestness |
2014-06-09 | sim: More rigorous clocking comments | Joel Hestness |
2014-06-04 | ext: Add a McPAT regression tester | Yasuko Eckert |
2014-06-03 | ext: McPAT interface changes and fixes | Yasuko Eckert |
2014-06-03 | ext: change McPAT to not force compile in 32-bit mode. | Yasuko Eckert |
2014-06-03 | ext: Redirect McPAT object files | Yasuko Eckert |
2014-05-31 | style: eliminate equality tests with true and false | Steve Reinhardt |
2014-05-24 | stats: changes due to recent o3 patch. | Nilay Vaish |
2014-05-23 | stats: changes due to o3 cpu and ruby message buffer patches | Nilay Vaish |
2014-05-23 | ruby: slicc: remove unused ids DNUCA* | Nilay Vaish |
2014-05-23 | ruby: remove old protocol documentation | Nilay Vaish |
2014-05-23 | ruby: message buffer: drop dequeue_getDelayCycles() | Nilay Vaish |
2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
2014-05-15 | config: remove unecessary assignment of etherlink interfaces | Anthony Gutierrez |
2014-05-12 | syscall emulation: clean up & comment SyscallReturn | Steve Reinhardt |
2014-05-12 | tests: update t1000 & pc-switcheroo-full stats | Steve Reinhardt |
2014-05-10 | tests: update eio ref outputs for new stats | Steve Reinhardt |
2014-05-09 | stats: Bump stats for the fixes, and mostly DRAM controller changes | Andreas Hansson |
2014-05-09 | config: Bump DRAM sweep bus speed to match DDR4 config | Andreas Hansson |
2014-05-09 | tests: Reflect name change in DRAM tests | Andreas Hansson |
2014-05-09 | mem: Update DDR3 and DDR4 based on datasheets | Andreas Hansson |
2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
2014-05-09 | mem: Simplify DRAM response scheduling | Andreas Hansson |
2014-05-09 | mem: Add precharge all (PREA) to the DRAM controller | Andreas Hansson |
2014-05-09 | mem: Remove printing of DRAM params | Andreas Hansson |
2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
2014-05-09 | mem: Merge DRAM latency calculation and bank state update | Andreas Hansson |
2014-05-09 | mem: Add tWR to DRAM activate and precharge constraints | Andreas Hansson |
2014-05-09 | mem: Merge DRAM page-management calculations | Andreas Hansson |
2014-05-09 | mem: Add DRAM power states to the controller | Andreas Hansson |
2014-05-09 | mem: Ensure DRAM refresh respects timings | Andreas Hansson |
2014-05-09 | mem: Make DRAM read/write switching less conservative | Andreas Hansson |
2014-04-17 | arm: Make sure UndefinedInstructions are properly initialized | Ali Saidi |
2014-04-17 | arm: allow DC instructions by default so SE mode works | Ali Saidi |
2014-04-17 | sim, arm: implement more of the at variety syscalls | Ali Saidi |
2014-05-09 | cpu: Useful getters for ActivityRecorder | Andrew Bardsley |
2014-05-09 | cpu: Add flag name printing to StaticInst | Andrew Bardsley |
2014-05-09 | cpu: Timebuf const accessors | Andrew Bardsley |
2014-05-09 | arm: Add branch flags onto macroops | Andrew Bardsley |
2014-05-09 | cpu: Allow setWhen on trace objects | Andrew Bardsley |
2014-05-09 | arm: add preliminary ISA splits for ARM arch | Curtis Dunham |
2014-05-09 | arch: teach ISA parser how to split code across files | Curtis Dunham |
2014-05-09 | config: Avoid generating a reference to myself for Parent.any | Geoffrey Blake |
2014-05-09 | arch, arm: Preserve TLB bootUncacheability when switching CPUs | Geoffrey Blake |