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AgeCommit message (Expand)Author
2007-05-26Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-26Get rid of GNU libelf and its autoconf nastiness and replaceNathan Binkert
2007-05-26Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-24Update to ply 2.3Nathan Binkert
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-22memtest.hh:Steve Reinhardt
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
2007-05-22memtest.py:Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-20Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-16Update the release notes for the 2.0 beta 3 releaseNathan Binkert
2007-05-15update all the regresstion tests for releaseAli Saidi
2007-05-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-15Merge zizzer:/bk/newmemAli Saidi
2007-05-15add an l2 cache option to se example configAli Saidi
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-14Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-14Merge zizzer:/bk/newmemAli Saidi
2007-05-14couple more bug fixes for intel nicAli Saidi
2007-05-14add uglyiness to fix dmasAli Saidi
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
2007-05-13Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
2007-05-13fix handling of atomic packetsAli Saidi
2007-05-11Move full CPU sim object stuff into the encumbered directoryNathan Binkert
2007-05-11Float should have a c++ param typeNathan Binkert
2007-05-11total should be the sum of the vector result of an operation,Nathan Binkert
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-10Merge zizzer:/bk/newmemAli Saidi
2007-05-10update for bus bridge updatesAli Saidi
2007-05-10add/update parameters for bus bridgeAli Saidi
2007-05-09couple of updates in the intel nicAli Saidi
2007-05-09update for new reschedule semanticsAli Saidi
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still const...Ali Saidi
2007-05-09Merge zeep:/z/saidi/work/m5.newmemAli Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-05-09fix the translating ports so it can add a page on a faultAli Saidi
2007-05-09Merge zizzer:/bk/newmemAli Saidi
2007-05-09bit_val was being used directly in the statement in return. If type B had few...Ali Saidi
2007-05-07update for partial write fix changesAli Saidi
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
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