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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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Commit message (
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Author
2006-12-30
Fix up previous commit to proper logic.
Kevin Lim
2006-12-29
Merge zizzer.eecs.umich.edu:/bk/newmem
Nathan Binkert
2006-12-29
Formatting
Nathan Binkert
2006-12-27
Merge zizzer:/bk/newmem
Ali Saidi
2006-12-27
Bug fixes in the TLB
Ali Saidi
2006-12-27
Compare legion and m5 tlbs for differences
Ali Saidi
2006-12-27
Change MemoryAccess dprintfs to print the data as well
Ali Saidi
2006-12-27
No need to use NULL, just use 0
Nathan Binkert
2006-12-26
Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
Kevin Lim
2006-12-24
Make sure that all of the bits in the result are set
Nathan Binkert
2006-12-24
remove some output formatting stuff that we don't use
Nathan Binkert
2006-12-22
Add options for setting the kernel to run and the
Nathan Binkert
2006-12-21
Fix copyright
Nathan Binkert
2006-12-21
Expose the C++ event queue to python via the python function
Nathan Binkert
2006-12-21
style
Nathan Binkert
2006-12-21
Create a wrapper function to more easily add swig stuff to the build
Nathan Binkert
2006-12-21
move the swig initialization calls from src/sim/main.cc to
Nathan Binkert
2006-12-20
don't use (*activeThreads).begin(), use activeThreads->blah().
Nathan Binkert
2006-12-20
Merge zizzer.eecs.umich.edu:/bk/newmem
Nathan Binkert
2006-12-20
<scold> Make sure that variables are always initalized! </scold>
Nathan Binkert
2006-12-19
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
Steve Reinhardt
2006-12-19
Merge zizzer:/bk/newmem
Ali Saidi
2006-12-19
fix twinx loads a little bit
Ali Saidi
2006-12-18
Streamline Cache/Tags interface: get rid of redundant functions,
Steve Reinhardt
2006-12-18
No need to template prefetcher on cache TagStore type.
Steve Reinhardt
2006-12-18
Get rid of generic CacheTags object (fold back into Cache).
Steve Reinhardt
2006-12-18
Fix unittest compiles
Nathan Binkert
2006-12-18
cast chars to int when we want to print integers so we get a number
Nathan Binkert
2006-12-18
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Ali Saidi
2006-12-17
Nate's utility for compiling m5
Nathan Binkert
2006-12-17
Utilities for doing a format check for some elements of proper
Nathan Binkert
2006-12-17
Compilation fixes.
Gabe Black
2006-12-17
Added in the extended twin load format
Gabe Black
2006-12-16
Merge zizzer:/bk/newmem
Gabe Black
2006-12-16
Merge zizzer:/bk/sparcfs/
Gabe Black
2006-12-16
Support for twin loads.
Gabe Black
2006-12-16
Compiler error fix.
Gabe Black
2006-12-15
Merge zizzer:/bk/newmem
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
small change to eliminate address range overlap.
Lisa Hsu
2006-12-15
little fixes i noticed while searching for reason for address range issues (b...
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
Merge zizzer:/bk/sparcfs
Lisa Hsu
2006-12-15
some small general fixes to make everythign work nicely with other ISAs, now ...
Lisa Hsu
2006-12-15
loadstore.isa:
Lisa Hsu
2006-12-15
tlb.cc:
Lisa Hsu
2006-12-15
Use my range_map to speed up findPort() in the bus. The snoop code could stil...
Ali Saidi
2006-12-15
Optimized the TLB translations with some caching
Ali Saidi
2006-12-14
flesh out twinx asis
Ali Saidi
2006-12-13
Split CachePort class into CpuSidePort and MemSidePort
Steve Reinhardt
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