gem5 - gem5

Age	Commit message (Expand)	Author
2016-12-19	arm: audit SCTLR	Curtis Dunham
2016-12-19	arm: remove SCTLR.FI	Curtis Dunham
2016-12-19	arm: update AArch{64,32} register mappings	Curtis Dunham
2016-12-19	mem: Make the BaseXBar public to not confuse Python wrappers	Andreas Sandberg
2016-12-19	python: Export periodicStatDump	Andreas Sandberg
2016-12-19	dev: Include DmaDevice in NULL builds	Andreas Sandberg
2016-12-19	python: Fix incorrect header in the DmaDevice wrapper	Andreas Sandberg
2016-12-19	sim: Remove redundant buildEnv import	Andreas Sandberg
2016-12-15	ruby: Detect garnet network-level deadlock.	Jieming Yin
2016-11-09	base: remove header file to prevent a macro name collision	Brandon Potter
2016-12-15	syscall_emul: implement fallocate	Brandon Potter
2016-12-15	syscall_emul: add support for x86 statfs system calls	Brandon Potter
2016-12-15	syscall_emul: extend sysinfo system call to include mem_unit	Brandon Potter
2016-12-06	dev: Fix race conditions at terminating dist-gem5 simulations	Gabor Dozsa
2016-12-06	arm, config: Add missing IOCache in bL config	Gabor Dozsa
2016-12-05	ruby: Remove RubyMemoryControl and associated files	Andreas Hansson
2016-12-05	stats: Update stats to reflect cache changes	Andreas Hansson
2016-12-05	config: Add an option to generate a random topology in memcheck	Nikos Nikoleris
2016-12-05	config: Add whole line accesses to improve memchecker's coverage	Nikos Nikoleris
2016-12-05	mem: Respond to InvalidateReq when the block is (pending) dirty	Nikos Nikoleris
2016-12-05	mem: Invalidate a blk when servicing the 1st invalidating target	Nikos Nikoleris
2016-12-05	mem: Allow non invalidating snoops on an InvalidateReq MSHR	Nikos Nikoleris
2016-12-05	mem: Don't use hasSharers in the snoopFilter for memory responses	Nikos Nikoleris
2016-12-05	mem: Always use InvalidateReq to service WriteLineReq misses	Nikos Nikoleris
2016-12-05	mem: Assert that the responderHadWritable is set only once	Nikos Nikoleris
2016-12-05	mem: Ensure InvalidateReq is considered isForward by MSHRs	Andreas Hansson
2016-12-05	mem: Make packet debug printing more uniform	Nikos Nikoleris
2016-12-05	cpu: Change traffic generators to use different values for writes	Nikos Nikoleris
2016-12-05	mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv	Nikos Nikoleris
2016-12-05	mem: Keep track of allocOnFill in the TargetList	Nikos Nikoleris
2016-12-05	mem: Add support for repopulating the flags of an MSHR TargetList	Nikos Nikoleris
2016-12-02	hsail: disable asserts to allow immediate operands i.e. 0 with loads	Brandon Potter
2016-12-02	hsail: add stub type and stub out several instructions	Brandon Potter
2016-12-02	hsail: add popcount type and generate popcount instructions	Brandon Potter
2016-12-02	hsail: add a wavesize case statement to register operand code	Brandon Potter
2016-12-02	hsail: generate mov instructions for more arith_types and bit_types	Brandon Potter
2016-12-02	hsail: remove the panic guarding function directives	Brandon Potter
2016-12-02	hsail: fix unsigned offset bug in address calculation	Tony Gutierrez
2016-12-02	ruby: Fix overflow reported by ASAN in MessageBuffer.	Matthew Poremba
2016-11-30	tests: Regression stats updated for recent patches	Jason Lowe-Power
2016-11-30	riscv: [Patch 8/5] Added some regression tests to RISC-V	Alec Roelke
2016-11-30	riscv: [Patch 7/5] Corrected LRSC semantics	Alec Roelke
2016-11-30	riscv: [Patch 6/5] Improve Linux emulation for RISC-V	Alec Roelke
2016-11-30	riscv: [Patch 5/5] Added missing support for timing CPU models	Alec Roelke
2016-11-30	riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A	Alec Roelke
2016-11-30	riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD	Alec Roelke
2016-11-30	riscv: [Patch 2/5] Added RISC-V multiply extension RV64M	Alec Roelke
2016-11-30	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	Alec Roelke
2016-11-30	mem: Split the hit_latency into tag_latency and data_latency	Sophiane Senni
2016-11-30	cpu: Remove branch predictor function predictInOrder	Jason Lowe-Power