summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2013-11-26kvm: Remove the unused hostFreq member from BaseKvmCPUAndreas Sandberg
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-11-15cpu: Fix Checker register index useAndreas Hansson
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-12sim: fix event priority name for debug-start optionAnthony Gutierrez
2013-11-01stats: Bump stats to match DRAM controller changesAndreas Hansson
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-11-01mem: Fix DRAM bank occupancy for streaming accessAni Udipi
2013-11-01mem: Schedule time for DRAM event taking tRAS into accountAni Udipi
2013-11-01mem: Add tRAS parameter to the DRAM controller modelAni Udipi
2013-11-01stats: Bump stats after shifting to SimpleMemoryAndreas Hansson
2013-11-01test: Use SimpleMemory for atomic full-system testsAndreas Hansson
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2013-10-31dev: Add 'OSC' oscillator sys control reg support to VersatileExpressMatt Evans
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
2013-10-31base: Add support for ipv6 into inet.hh/inet.ccGeoffrey Blake
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-31sim: added option to serialize SimLoopExitEventDam Sunwoo
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-10-31arm: fix m5ops binary for ARM and add m5fail.Ali Saidi
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2013-10-17arm: Add a 'clear PPI' method to gic_pl390Matt Evans
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
2013-10-17dev: Add option to disable framebuffer .bmp dump in run folderDam Sunwoo
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
2013-10-17util: Streamline .apc project convertsion scriptDam Sunwoo