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2006-08-15Update release files.Steve Reinhardt
README: Add brief build instructions for the impatient. A few minor fixes. RELEASE_NOTES: Change date; add beta disclaimer. --HG-- extra : convert_revision : d31af687c657feb36a2694ef9f0abd67390c7023
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
--HG-- extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem src/cpu/static_inst.hh: SCCS merged --HG-- extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-15Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into ↵Gabe Black
arch/alpha/pagetable.hh and fixing up some includes --HG-- extra : convert_revision : 02a47fa62b17245763314890beb68339c789d18f
2006-08-15More cleanup for release.Steve Reinhardt
--HG-- extra : convert_revision : 94b45da5d1a658c4d0f87c73ce72facc9da8d981
2006-08-14Fix up doxygen.Steve Reinhardt
--HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-08-14Changes for release.Steve Reinhardt
README: s/m5.eecs.umich.edu/www.m5sim.org/ whack mentions of "CD distribution" RELEASE_NOTES: Set date of 2.0 beta release Fix typo --HG-- extra : convert_revision : 5baa113a98f89dbf56f60adb4513ca22b63673b1
2006-08-14Changed the size parameter from int to int64_tGabe Black
--HG-- extra : convert_revision : a19404bdc3a6434fe28f8aa278dc6addf764be22
2006-08-11Started to add support for O3 for sparc.Gabe Black
--HG-- extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
2006-08-11Changed the compiler guards to say SPARCGabe Black
--HG-- extra : convert_revision : e79964148c7fb7075627f46add6687f6cd0ee241
2006-08-11Added code to support setting up all of the auxillieary vectors configured ↵Gabe Black
by the sparc linux elf loader. src/arch/sparc/process.cc: All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow. --HG-- extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
2006-08-11#include of iostream needed.Gabe Black
--HG-- extra : convert_revision : d31bb943ab25103cf715159054df318a5b88abc9
2006-08-11Adjusted the decoder a little.Gabe Black
--HG-- extra : convert_revision : 5bdbe00342837ae4caacb3ad86c7becca36ba6ce
2006-08-11Started adding a system to output data after every instruction.Gabe Black
src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. --HG-- extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵Gabe Black
created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
2006-08-11make test3.py usable again ... I guess I should fix up test4 and test5 too???Korey Sewell
Also, What happened to the "lets make real names for these tests" thing we were talking about? Is test1 - test(n) OK now? --HG-- extra : convert_revision : 60716e41ecc79a78241be383ab3cae4b9e382335
2006-08-10really confused about this license but OK...Korey Sewell
--HG-- extra : convert_revision : 85e40593e344b9eff325061630db27d178937258
2006-07-27Clean up some more config stuff.Kevin Lim
configs/common/FSConfig.py: Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself. configs/test/fs.py: Update for changed code. src/python/m5/__init__.py: Put makeList into m5. --HG-- extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
2006-07-27Update ref stats.Kevin Lim
tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27Output the command line.Kevin Lim
src/python/m5/main.py: Output the command line being used. --HG-- extra : convert_revision : 51dadb0ef79ca1e8bbb5a3bd64110071c30ade0d
2006-07-27Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 70221af596bddbfcc40646d03f175ef5e4b75909
2006-07-27Need config read/write latency.Kevin Lim
--HG-- extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
2006-07-26MIPS ISA runs 'hello world' in O3CPU ...Korey Sewell
src/arch/mips/isa/base.isa: special case syscall disasembly... maybe give own instruction class? src/arch/mips/isa/decoder.isa: add 'IsSerializeAfter' flag for syscall src/cpu/o3/commit.hh: Add skidBuffer to commit src/cpu/o3/commit_impl.hh: Use skidbuffer in MIPS ISA src/cpu/o3/fetch_impl.hh: Print name out when there is a fault src/cpu/o3/mips/cpu_impl.hh: change comment --HG-- extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
2006-07-26Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 3bb2cdd9b286e7f0235fb5fd5099b89775e05a10
2006-07-26Added alot of fp instructions, and some impdep instructions.Gabe Black
--HG-- extra : convert_revision : cc703919b59e674044ae370a65dc03deece6d69e
2006-07-26Now ignore sigactionGabe Black
src/arch/sparc/isa/operands.isa: Added the GSR register as a control register --HG-- extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
2006-07-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It ↵Korey Sewell
builds, runs, and gets very very close to completing the hello world succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh! Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... ) src/arch/alpha/isa/mem.isa: spacing src/arch/mips/faults.cc: src/arch/mips/faults.hh: Gabe really authored this src/arch/mips/isa/decoder.isa: add StoreConditional Flag to instruction src/arch/mips/isa/formats/basic.isa: Steven really did this file src/arch/mips/isa/formats/branch.isa: fix bug for uncond/cond control src/arch/mips/isa/formats/mem.isa: Adjust O3CPU memory access to use new memory model interface. src/arch/mips/isa/formats/util.isa: update LoadStoreBase template src/arch/mips/isa_traits.cc: update SERIALIZE partially src/arch/mips/process.cc: src/arch/mips/process.hh: no need for this for NOW. ASID/Virtual addressing handles it src/arch/mips/regfile/misc_regfile.hh: add in clear() function and comments for future usage of special misc. regs src/cpu/base_dyn_inst.hh: add in nextNPC variable and supporting functions. add isCondDelaySlot function Update predTaken and mispredicted functions src/cpu/base_dyn_inst_impl.hh: init nextNPC src/cpu/o3/SConscript: add MIPS files to compile src/cpu/o3/alpha/thread_context.hh: no need for my name on this file src/cpu/o3/bpred_unit_impl.hh: Update RAS appropriately for MIPS src/cpu/o3/comm.hh: add some extra communication variables to aid in handling the delay slots src/cpu/o3/commit.hh: minor name fix for nextNPC functions. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rename_impl.hh: Fix necessary variables and functions for squashes with delay slots src/cpu/o3/cpu.cc: Update function interface ... adjust removeInstsNotInROB function to recognize delay slots insts src/cpu/o3/cpu.hh: update removeInstsNotInROB src/cpu/o3/decode.hh: declare necessary variables for handling delay slot src/cpu/o3/dyn_inst.hh: Add in MipsDynInst src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/rename.hh: declare necessary variables and adjust functions for handling delay slot src/cpu/o3/inst_queue.hh: src/cpu/simple/base.cc: no need for my name here src/cpu/o3/isa_specific.hh: add in MIPS files src/cpu/o3/scoreboard.hh: dont include alpha specific isa traits! src/cpu/o3/thread_context.hh: no need for my name here, i just rearranged where the file goes src/cpu/static_inst.hh: add isCondDelaySlot function src/cpu/o3/mips/cpu.cc: src/cpu/o3/mips/cpu.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/mips/dyn_inst.cc: src/cpu/o3/mips/dyn_inst.hh: src/cpu/o3/mips/dyn_inst_impl.hh: src/cpu/o3/mips/impl.hh: src/cpu/o3/mips/params.hh: src/cpu/o3/mips/thread_context.cc: src/cpu/o3/mips/thread_context.hh: MIPS file for O3CPU...mirrors ALPHA definition --HG-- extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
2006-07-23Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : f6a68bbf8aad9be54ff24310b3e51eaed9abb8b5
2006-07-23Added myself to the authors list.Gabe Black
--HG-- extra : convert_revision : d90154159473ed93c5b50cf3221e132eda242852
2006-07-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 45650c90385b4e13e79ccf271a30bb55552b380f
2006-07-23Fix up test.pyKevin Lim
configs/test/test.py: Fix up this config. --HG-- extra : convert_revision : e15071ee27b860cc3ad79277aa61f3e6bb7405d3
2006-07-22Reorganized SPARC binariesGabe Black
--HG-- rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22Fixed subtract with carry, and started some work with floating point.Gabe Black
src/arch/sparc/isa/decoder.isa: fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point. src/arch/sparc/isa/operands.isa: Added in floating point operands, and changed the numbering of operands. src/arch/sparc/regfile.hh: Fixed some memory errors related to floating point. --HG-- extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
2006-07-22Last minute check in. Very few functional changes other than some minor ↵Kevin Lim
config updates. Also include some recently generated stats. SConstruct: Make test CPUs option non-sticky. configs/common/FSConfig.py: Be sure to set the memory mode. configs/test/fs.py: Wrong string. tests/SConscript: Only test valid CPUs that have been compiled in. tests/test1/ref/alpha/atomic/config.ini: tests/test1/ref/alpha/atomic/config.out: tests/test1/ref/alpha/atomic/m5stats.txt: tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/config.ini: tests/test1/ref/alpha/detailed/config.out: tests/test1/ref/alpha/detailed/m5stats.txt: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/config.ini: tests/test1/ref/alpha/timing/config.out: tests/test1/ref/alpha/timing/m5stats.txt: tests/test1/ref/alpha/timing/stdout: Update output. --HG-- extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-21Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: Hand merge. --HG-- extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21Rearrange the FS configs to be more shared. Also check in the full-system ↵Kevin Lim
tests. Reference stats coming soon. configs/test/fs.py: Pull out a lot of common code and put it into configs/common/FSConfig.py. --HG-- extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21Missed some files in a previous check-in. Also check-in the SMT tests. ↵Kevin Lim
Reference stats will be coming soon. --HG-- extra : convert_revision : c2f7ea613f350e62395f2b50e4c8cc21c6960a22
2006-07-21Minor functionality updates.Kevin Lim
SConstruct: Include an option to specify the CPUs being tested. src/cpu/SConscript: Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker. src/python/m5/objects/O3CPU.py: Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used. tests/SConscript: Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on. --HG-- extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
2006-07-21Some reorganization. Options are all handled at the user level script. ↵Kevin Lim
Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs. --HG-- rename : configs/test/SysPaths.py => configs/common/SysPaths.py extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-20Fixed a glitch in the disassembly output.Gabe Black
--HG-- extra : convert_revision : 833aa358b12ac987e0ab467708425c17e5a8fdb7
2006-07-20Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 0c696374b19b27c0bd50ffa7f75117b1e211e4bc
2006-07-20Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c7fedc68996f2f6cbfb70baebf7c87e0736da883
2006-07-20Move PioPort timing code into Simple Timing Port objectAli Saidi
Make PioPort use it Make Physical memory use it as well src/SConscript: Add timing port to sconscript src/dev/io_device.cc: src/dev/io_device.hh: Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory src/mem/physical.cc: src/mem/physical.hh: use a simple timing port stuff instead of rolling our own here --HG-- extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
Add a max time option in seconds and a single system root clock be 1THz configs/test/fs.py: Add a max time option in seconds and a single system root clock be 1THz src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Enforce the timing cpu ticking at it's clock rate --HG-- extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-19Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 8c747208d72ffbb0160a2ad4a75383420debdf83
2006-07-19Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c5dbee4ba46fae1edba732f4bd05ef984a46d088
2006-07-19Change the device latency here to a latency rather than a TickAli Saidi
src/python/m5/objects/Device.py: src/python/m5/objects/Pci.py: Change the default here to a latency rather than a Tick --HG-- extra : convert_revision : b9366dd89646cea27a836baf249ac2da38c1809f
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
src/cpu/checker/cpu.hh: Don't count checker's instructions towards total instructions committed. src/python/m5/objects/Root.py: Set default clock to 1 THz. --HG-- extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-01 19:53:13 +0000