Age | Commit message (Collapse) | Author |
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corresponding to an IPR is readable or writable.
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code all over the place.
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the miscreg index of a specific IPR.
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functions.
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more neutral names.
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Accidentally committed this last time
configs/common/FSConfig.py:
Accidentally committed this last time
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import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache
configs/common/Simulation.py:
Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
import Caches
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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confused otherwise, oops.
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this script from.
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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configs/common/Options.py:
make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
add some comments and also make the warmup period an option.
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src/cpu/simple/base.cc:
Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
Serialize the microPC and nextMicroPC
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in the future for micro insts.
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src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
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the integer microcode register.
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
configs/example/fs.py:
configs/example/se.py:
hand merge
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configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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