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AgeCommit message (Expand)Author
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-27ruby: set the is_icache param for cachesMalek Musleh
2012-10-27Ruby: Use block size in configuring directory bits in addressJason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-25arm: Use table walker clock that is inherited from CPUAndreas Hansson
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
2012-10-23dev: Remove zero-time loop in DMA timing sendAndreas Hansson
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15memtest: move check on outstanding requestsNilay Vaish
2012-10-15 ruby: register multiple memory controllersNilay Vaish
2012-10-15ruby: remove AbstractMemOrCacheNilay Vaish
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Mem: Fix incorrect logic in bus blocksize checkAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-11Doxygen: Update the version of the DoxyfileAndreas Hansson
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-10-02ruby: remove some unused things in sliccNilay Vaish