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AgeCommit message (Expand)Author
2018-01-05arch-riscv: Ignore set_robust_list and get_robust_list syscallsTuan Ta
2018-01-05arch-riscv: Add an implementation of set_tid_address syscall in RISCVTuan Ta
2018-01-05arch-riscv: Correct syscall argument reg countAlec Roelke
2018-01-04arch-riscv: Remove "magic" syscall number constantAlec Roelke
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
2017-12-23riscv,x86: Stop using the arch Nop machine instruction unnecessarily.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-14ext: Upgrade PyBind11 to version 2.2.1Jason Lowe-Power
2017-12-14x86: Use operand size 4 when it would be 2 for cmpxchg8b.Gabe Black
2017-12-13scons, tests: Fix occasional linking errorAndreas Sandberg
2017-12-13scons, tests: Add support for GTest XML generationAndreas Sandberg
2017-12-13scons: Make sure GTests have the right environment variablesAndreas Sandberg
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-13x86: Rework how "split" loads/stores are handled.Gabe Black
2017-12-13base: Add endianness conversion functions for std::array types.Gabe Black
2017-12-12tests: Turn fbtest into a gtest and move it to src/base.Gabe Black
2017-12-12tests: Move the cprintftest unit test into src/base.Gabe Black
2017-12-12tests: Convert the cprintf unit test into a gtest.Gabe Black
2017-12-12tests: Move the trietest unit test into base.Gabe Black
2017-12-12tests: Plumb dumps of the test trie into the gtest macros.Gabe Black
2017-12-12tests: Convert the trie unit test into a gtest.Gabe Black
2017-12-12tests: Add an implementation of the Logger interface for use gtests.Gabe Black
2017-12-12misc: Rework the logging functions.Gabe Black
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
2017-12-08arm: Change access permission in TPIDRURO and TPIDRURWGiacomo Travaglini
2017-12-08x86,misc: add additional info on faulting X86 instruction, fetched PCMatt Sinclair
2017-12-07tests: Accept SourceFilters as sources for GTest.Gabe Black
2017-12-07tests: Add a pseudo target to run all the unit tests for build/variant.Gabe Black
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
2017-12-06misc: Update MAINTAINERS with learning-gem5 tagJason Lowe-Power
2017-12-06base: Split out the pixel class in framebuffer.(cc|hh).Gabe Black