gem5 - gem5

Age	Commit message (Expand)	Author
2006-12-16	Merge zizzer:/bk/newmem	Gabe Black
2006-12-16	Switch the endianness of data that's forwarded. This is the same sort of prob...	Gabe Black
2006-12-16	Make fetch detect when a branch is happening, rather than trying to compute w...	Gabe Black
2006-12-16	Accidently "cleaned" away the NPC parameter to the constructor.	Gabe Black
2006-12-16	Don't have "predict" set the predicted target of the instruction. Do that exp...	Gabe Black
2006-12-16	Add in constants which let you explicitly check if endian conversion would do...	Gabe Black
2006-12-16	Add in capability to return to unblocking after a squash. This is needed beca...	Gabe Black
2006-12-16	Make sure endian conversion is done on the memory data when it's just set to ...	Gabe Black
2006-12-16	Make the decoder use the new setup in the dyninsts for branch prediction.	Gabe Black
2006-12-16	Made branch delay slots get squashed, and passed back an NPC and NNPC to star...	Gabe Black
2006-12-16	Added a predicted NPC field, explicitly stored whether the instruction was pr...	Gabe Black
2006-12-16	Made changes to CWP be non speculative.	Gabe Black
2006-12-16	Changes to the isa_parser and affected files to fix an indexing problem with ...	Gabe Black
2006-12-15	Merge zizzer:/bk/newmem	Lisa Hsu
2006-12-15	Merge zizzer:/bk/sparcfs	Lisa Hsu
2006-12-15	small change to eliminate address range overlap.	Lisa Hsu
2006-12-15	little fixes i noticed while searching for reason for address range issues (b...	Lisa Hsu
2006-12-15	Merge zizzer:/bk/sparcfs	Lisa Hsu
2006-12-15	Merge zizzer:/bk/sparcfs	Lisa Hsu
2006-12-15	some small general fixes to make everythign work nicely with other ISAs, now ...	Lisa Hsu
2006-12-15	loadstore.isa:	Lisa Hsu
2006-12-15	tlb.cc:	Lisa Hsu
2006-12-15	Use my range_map to speed up findPort() in the bus. The snoop code could stil...	Ali Saidi
2006-12-15	Optimized the TLB translations with some caching	Ali Saidi
2006-12-14	flesh out twinx asis	Ali Saidi
2006-12-13	Split CachePort class into CpuSidePort and MemSidePort	Steve Reinhardt
2006-12-13	Merge zizzer:/bk/newmem	Lisa Hsu
2006-12-13	fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.	Lisa Hsu
2006-12-13	Merge zizzer:/bk/newmem	Lisa Hsu
2006-12-13	Merge zizzer:/bk/sparcfs	Lisa Hsu
2006-12-12	Merge zizzer:/bk/newmem	Lisa Hsu
2006-12-12	Merge zizzer:/bk/newmem/	Gabe Black
2006-12-12	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-12-12	Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)	Ali Saidi
2006-12-12	Allow for multiple redirects to happen on a single cycle (only the one for th...	Kevin Lim
2006-12-12	Rename the StaticInst-based (read\|set)(Int\|Float)Reg methods to (read\|set)(In...	Steve Reinhardt
2006-12-12	If no tests are specified for regression, just build the binaries	Steve Reinhardt
2006-12-12	Get rid of unused lock code.	Steve Reinhardt
2006-12-11	Fix up in case a req hasn't yet been generated for this instruction (if there...	Kevin Lim
2006-12-11	Fix for fetch to use the icache's block size to generate proper access size.	Kevin Lim
2006-12-10	Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head	Steve Reinhardt
2006-12-10	Reorder CacheTags members for better cache performance.	Steve Reinhardt
2006-12-10	Get rid of dummy 'hello world' outputs.	Steve Reinhardt
2006-12-10	Delete parser reference outputs so that test will no longer be run.	Steve Reinhardt
2006-12-10	Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2	Steve Reinhardt
2006-12-10	Add '-j' option directly to regress script (passed to scons).	Steve Reinhardt
2006-12-09	Merge vm1.(none):/home/stever/bk/newmem-head	Steve Reinhardt
2006-12-09	fix lisa's hand merge	Ali Saidi
2006-12-09	Merge zizzer:/bk/sparcfs	Ali Saidi
2006-12-09	Allocate the correct number of global registers	Ali Saidi