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2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual. This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces. The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done. A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem. Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
This removes a dependence on the ISA. Change-Id: I01013bc70558f0831327213912bcac11258066a6 Reviewed-on: https://gem5-review.googlesource.com/6824 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
This can be used whenever generic code needs a filler instruction that doesn't do anything. Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f Reviewed-on: https://gem5-review.googlesource.com/6823 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
This patch fixes the WFx trapping behaviour by introducing the arm arm v8 pseudocode functions: checkForWFxTrap32 and checkForWFxTrap64 Change-Id: I3db0d78b5c4ad46860e6d199c2f2fc7b41842840 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
If undefined instruction has to be routed to EL2, the HSR register must change the HSR.EC and HSR.ISS accordingly, which means not using the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0) Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6621 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
The previously introduced method was missing the machInst value to be masked. Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964 Reviewed-on: https://gem5-review.googlesource.com/6822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
This patch is introducing some methods in StaticInst so that is possible to get the instruction size in byte of the instruction (can be 2 bytes in Thumb) and the correct opcode (The machInst field contains some appended metadata) Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6781 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
Cosmetic fix: prefer static_cast rather than reinterpret_cast in hierarchy. Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6761 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
Added the ExitGen to the TrafficGenerator which allows an EXIT state to be added to the TrafficGen configuration file. Entering this state will cause the simulation to exit immediately. Please note that if multiple TrafficGen instances have an EXIT state, the first of these to be encountered will cause the simulation to terminate. Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5723 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013 Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5722 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-14arch-riscv: Define AT_RANDOM properlyAlec Roelke
According to the getauxval(3) man page, the AT_RANDOM aux value should be a pointer to 16 random bytes. In the initial implementation of RISC-V, this was based on spike's program stack setup, which copied the program header table there instead. This patch changes the implementation to use the proper 16 random bytes, making it compatible with some RISC-V programs that use custom linker scripts. Change-Id: Idaae7f19bf3ed3fd06d293e5e9c0b6f778270eb2 Reviewed-on: https://gem5-review.googlesource.com/6681 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-14arch-riscv: Increase maximum stack sizeAlec Roelke
This patch increases the maximum stack size of RISC-V, which should help to reduce problems with programs that allocate large amounts of data on the stack or do many small allocations. Change-Id: I1d760050229b12f01a4a8f24c047b587299fef6d Reviewed-on: https://gem5-review.googlesource.com/6661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-14ext: Upgrade PyBind11 to version 2.2.1Jason Lowe-Power
This upgrade is necessary for pybind to build with GCC 7.2. We still need to add the patch for stl.h. MSC_FULL_VER change is no longer needed. See https://gem5-review.googlesource.com/c/public/gem5/+/2230 Change-Id: I806729217d022070583994c2dfcaa74476aef30f Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5801 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-14x86: Use operand size 4 when it would be 2 for cmpxchg8b.Gabe Black
This means the instruction is treated as cmpxchg8b when the effective operand size is 16 bits. Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab Reviewed-on: https://gem5-review.googlesource.com/6603 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-13scons, tests: Fix occasional linking errorAndreas Sandberg
There are some cases where scons incorrectly adds the same object multiple times to the linker command line. This seems to be caused by the test's source list being updated in place when determining test framework dependencies. Fix this by explicitly copying the source list and manipulate the copy. Without this change, the following command fails: scons ./build/ARM/unittests.opt/base/pixeltest.xml Whereas this command succeeds: scons ./build/ARM/base/pixeltest.opt Change-Id: I642efdf9d62a5478e49ba51efe1a3a5ba453e21f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13scons, tests: Add support for GTest XML generationAndreas Sandberg
The GTest framework supports result generation in XML (JUnit). Enable this by creating unit test specific targets in the build/${BUILD_OPTS}/unittests.${VARIANT} directory. Targets in the directory use the following naming convention: ${SRC_PATH}/${TEST_NAME}.xml For example, the opt version of the bitunion test built for ARM would have this path: build/ARM/unittests.opt/base/bituniontest.xml Change-Id: I174dff16817734db05b08ce1d5bcf52e8697bbac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6624 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13scons: Make sure GTests have the right environment variablesAndreas Sandberg
SCons currently scrubs the environment variables used by GTests too aggressively. This breaks systems where libraries are installed in non-standard locations that need to be specified in LD_LIBRARY_PATH. Run said tests in the gtest_env SCons environment which white-lists the important environment variables. Change-Id: I5fc8fb5e51f09644dc976ee97b21c78ab349bf7d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6623 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
Neither of these were used, particularly memAccInst. Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc Reviewed-on: https://gem5-review.googlesource.com/6601 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-13x86: Rework how "split" loads/stores are handled.Gabe Black
Explicitly separate the way the data is represented in the underlying representation from how it's represented in the instruction. In order to make the ISA parser happy, the Mem operand needs to have a single, particular type. To handle that with scalar types, we just used uint64_ts and then worked with values that were smaller than the maximum we could hold. To work with these new array values, we also use an underlying uint64_t for each element. To make accessing the underlying memory system more natural, when we go to actually read or write values, we translate the access into an array of the actual, correct underlying type. That way we don't have non-exact asserts which confuse gcc, or weird endianness conversion which assumes that the data should be flipped 8 bytes at a time. Because the functions involved are generally inline, the syntactic niceness should all boil off, and the final implementation in the binary should be simple and efficient for the given data types. Change-Id: I14ce7a2fe0dc2cbaf6ad4a0d19f743c45ee78e26 Reviewed-on: https://gem5-review.googlesource.com/6582 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-13base: Add endianness conversion functions for std::array types.Gabe Black
These swap the endianness of each element within the array individually. They probably obsolute the Twin(32|64)_t types which I believe were used for SPARC. Change-Id: Ic389eb24bdcdc0081068b0c5a37abdf416f6c924 Reviewed-on: https://gem5-review.googlesource.com/6581 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12tests: Turn fbtest into a gtest and move it to src/base.Gabe Black
Change-Id: I9ca57e24f27e0eb747d1f27262972a8abcd10fc8 Reviewed-on: https://gem5-review.googlesource.com/6342 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12tests: Move the cprintftest unit test into src/base.Gabe Black
That way it will live alongside the code it tests. Change-Id: I00baad2206870a4619b7cee792a1d4c303dad04d Reviewed-on: https://gem5-review.googlesource.com/6324 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12tests: Convert the cprintf unit test into a gtest.Gabe Black
Change-Id: I0f78a202d1f5fd29cda94ca93b540618831fe898 Reviewed-on: https://gem5-review.googlesource.com/6323 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12tests: Move the trietest unit test into base.Gabe Black
This puts it alongside trie.hh, the header file it tests. Change-Id: Id8ca0c1d68bdc01807c5ba4b51c0142b1221385d Reviewed-on: https://gem5-review.googlesource.com/6281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2017-12-12tests: Plumb dumps of the test trie into the gtest macros.Gabe Black
With this change, when one of the tests fails, it will output a dump of the trie data structure, making it a little easier to tell what happened. Change-Id: I0816ed727ef0b50fefd7ec485356b4fe8790bfe1 Reviewed-on: https://gem5-review.googlesource.com/6267 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-12tests: Convert the trie unit test into a gtest.Gabe Black
Change-Id: Idcf60260d9bda1b8ef5b6f5d59b74ca218395f0c Reviewed-on: https://gem5-review.googlesource.com/6265 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2017-12-12tests: Add an implementation of the Logger interface for use gtests.Gabe Black
On exiting log types (panic and fatal), the message is set to an ADD_FAILURE_AT macro, and the test is exited by throwing an otherwise unexpected exception. On non-exiting log types, the message is sent to the SUCCEEDED macro which currently doesn't output anything. Change-Id: I1bb569e6cb8308dbc4c3e04eea7a962bd2b1ddd8 Reviewed-on: https://gem5-review.googlesource.com/6264 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12misc: Rework the logging functions.Gabe Black
Removed the "verbose" switch which wasn't used. Replaced the "get(LogLevel)" function with a get for each level. The parameter was always constant, so we can just call the right function at the right time. Made the "exit" behavior of panic/fatal a part of the logging implementation so that it can be overridden, and corrected a comment which said that both fatal and panic called ::abort(). Got rid of the printEpilogue function by reworking the print() methods. The subclasses of Logger can now override a "log" function which takes a composed message, letting the Logger class centralize how the message is put together and leaving the actual output mechanism to the subclass. Unfortunately there wasn't a way to tell gcc that the panic/fatal macros wouldn't return, so there needed to be an exit_helper wrapper function which calls the actual logger exit function. That can be marked as noreturn, unlike the virtual exit function. If the exit function does return, the wrapper will call ::abort(), placating gcc and ensuring that even if exit isn't implemented properly, exit_helper will still not return. That also provides a handy default implementation. Change-Id: I66d0cebd59f1127db980f3b565dbdf60687d8862 Reviewed-on: https://gem5-review.googlesource.com/6263 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa parameter, switch_cpus should have the ISA copied. This fixes a fatal error in BaseCPU when restoring from a checkpoint. Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/6241 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-08arm: Change access permission in TPIDRURO and TPIDRURWGiacomo Travaglini
This patch corrects the TPIDRURO and TPIDRURW access flags: TPIDRURO is now readable in secure user mode, an TPIDRURW is readable and writable in secure user mode. Change-Id: I6293d9a3bcc7adc0f655bf98d29aca51eca5a002 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6381 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-08x86,misc: add additional info on faulting X86 instruction, fetched PCMatt Sinclair
Print faulting instruction for unmapped address panic in faults.cc and print extra info about corresponding fetched PC in base.cc. Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f Reviewed-on: https://gem5-review.googlesource.com/6461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-07tests: Accept SourceFilters as sources for GTest.Gabe Black
This change introduces the idea of a SourceFilter which is an object that can filter a SourceList and which can be composed with other SourceFilters using | and & operators. This means a filter can be constructed ahead of time, possibly before all sources have been discovered, and then later applied to any SourceList necessary. This change also modifies GTest so that it accepts SourceFilters in addition to normal source files. These filters will be applied to the final list of all sources, and the result included in the build for that test. By default, gtests will build in all sources tagged with 'gtest lib'. This change also introduces the keyword argument "skip_lib" which will exclude those files. They can then be left out entirely, or they can be re-included as part of a more elaborate filter. That would be useful if someone wanted to write a unit test for, for instance, the warn, etc. macros which rely on the gtest logging support. Those classes could be replaced by something under the control of the unit test, while still including the rest of the gtest library. Change-Id: I13a846dc884b86b9fdcaf809edefd57bb4168b8e Reviewed-on: https://gem5-review.googlesource.com/6262 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-07tests: Add a pseudo target to run all the unit tests for build/variant.Gabe Black
Telling scons to build build/${BUILD_OPTS}/unittests.${VARIANT} will get it to build and run all googletest based unit tests under the ${BUILD_OPTS} build options (ARM, ALPHA, X86, etc.), and compiled with the flags, etc., for the ${VARIANT} variant (ie. opt, debug, etc.). This will make it easy to run the unit tests without having to actually know where they are, what tests are available, etc. This target is called unittests* and not something based on gtest or googletest since it's my intention for all unit tests to be based on googletest, making the distinction unnecessary. Since the target is essentially part of the external interface for scons, I wanted to name it something general so it'll be less likely that we have to change it. Change-Id: I8fdec768d821974309c92a2ce4c96dce7df24fa5 Reviewed-on: https://gem5-review.googlesource.com/6282 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-07arch-riscv: Move compressed ops out of ISAAlec Roelke
This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Reviewed-on: https://gem5-review.googlesource.com/6026 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-06x86: Split apart x87's FSW and TOP, and add a missing break.Gabe Black
The FSW and TOP values are technically part of the same register, but they have very different behaviors. One of them can be renamed and float along without affecting global state, while the other requires serialization. They just need to *look* like the same register when read by the user. Also, there was a missing break in setMiscRegNoEffect. Change-Id: If58de0f566f65068208240f4001209fb9e1826d6 Reviewed-on: https://gem5-review.googlesource.com/6441 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-06misc: Update MAINTAINERS with learning-gem5 tagJason Lowe-Power
Change-Id: Ic91fb1d9b2c3c42946cb84c1ec52d9376d4e50b4 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/6422 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-06base: Split out the pixel class in framebuffer.(cc|hh).Gabe Black
These are really two separate things. Also, while it's realitively straightforward to write a unit test for the pixel conversion code, the framebuffer object is serializable and brings in more dependencies. Change-Id: If954caeb0bfedb1002cfb1a7a115a00c90d56d19 Reviewed-on: https://gem5-review.googlesource.com/6341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-06base: Handle zero fill in cprintf when printing floats.Gabe Black
The fill_zero flag was being followed for ints, but not for floats. This makes the cprintf unit test pass. Change-Id: I4d17a3c9327aea05e0a3c81be1886c0c9256f03c Reviewed-on: https://gem5-review.googlesource.com/6322 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-06tests: Fix the source file for the cprintftime test.Gabe Black
It was using the source file for the cprintftest unit test. Change-Id: I534798e892ad55cef2f48be2ba9d732aa1993819 Reviewed-on: https://gem5-review.googlesource.com/6321 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-06scons: Several fixes having to do with tags and sets.Gabe Black
There were a few places where tags weren't being converted to sets correctly which unfortunately only manifested when called in certain ways. This would be a pretty reasonable place to add some python unit tests... Change-Id: I87509369b4ec6f702b7521e52bf63701a87ec436 Reviewed-on: https://gem5-review.googlesource.com/6261 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-06scons: Track and reuse object nodes for a given source file.Gabe Black
scons gets upset if two different environments are used to set up a particular object file. This change adds two dicts to the SourceFile class, one for static and one for shared object files, which are keyed off of the appropriate suffix. If a suffix hasn't been set up yet, a new node of the appropriate type is set up and stored in the cache, and then whatever is in the cache (new or old) is returned. Change-Id: Ice4b4fc728b438a4d3316c3ff6667c0480d2a6d7 Reviewed-on: https://gem5-review.googlesource.com/6224 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-05x86: LOOP's operand size defaults to 64 bits in 64 bit mode.Gabe Black
The microcode for those instructions needs a directive which overrides that setting in the instructions emulation environment. Reported-by: Matt Sinclair <mattdsinclair@gmail.com> Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967 Reviewed-on: https://gem5-review.googlesource.com/6301 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-12-05learning-gem5: Fix missing misc.hh in hello_object.ccHanhwi Jang
misc.hh has been renamed in commit 1088f0c4ac3999fc3c363cc51daef4cfb360a2bd Change-Id: Ic4f8c6423e6a5466f8d924e793a24f62bb4eca9c Reviewed-on: https://gem5-review.googlesource.com/6361 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
This patch adds support for decoding and executing the following ARMv8 cache maintenance instructions by Virtual Address: * dc civac: Clean and Invalidate by Virtual Address to the Point of Coherency * dc cvac: Clean by Virtual Address to the Point of Coherency * dc cvau: Clean by Virtual Address to the Point of Unification * dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5060 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
This patch adds support for the ARMv7 cache maintenance intructions: * mcr dccmvac cleans a VA to the PoC * mcr dcimvac invalidates a VA to the PoC * mcr dccimvac cleans and invalidates a VA to the PoC * mcr dccmvau cleans a VA to the PoU Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5059 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem-ruby: Prevent ruby from crashing on CMOsNikos Nikoleris
Ruby has no support for cache maintenace operations. As a workaround, after printing a warning, we treat them as no-ops in the memory system and respond immediately without handling them. There should be workarounds in the memory system already that allow execution to proceed without the requirement for cache maintenance operations. Change-Id: I125ee4fa37b674c636d87f2d9205bbc1a74da101 Reviewed-on: https://gem5-review.googlesource.com/5057 Reviewed-by: Jieming Yin <bjm419@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 18:37:25 +0000