| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-11-18 | ruby: Hammer ruby configuration support | Brad Beckmann | |
| 2009-11-18 | ruby: Changes necessary to get the hammer protocol to work in GEM5 | Brad Beckmann | |
| 2009-11-18 | ruby: added the original hammer protocols from old ruby | Brad Beckmann | |
| 2009-11-18 | ruby: returns the number of LLC needed for broadcast | Brad Beckmann | |
| Added feature to CacheMemory to return the number of last level caches. This count is need for broadcast protocols such as MOESI_hammer. | |||
| 2009-11-18 | ruby: cache configuration fix to use bytes | Brad Beckmann | |
| Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races. | |||
| 2009-11-18 | ruby: fix CacheMemory destructor | Brad Beckmann | |
| 2009-11-18 | ruby: split CacheMemory.hh into a .hh and a .cc | Brad Beckmann | |
| 2009-11-18 | ruby: Added default names to message buffers | Brad Beckmann | |
| Added default names to message buffers created by the simple network. | |||
| 2009-11-18 | ruby: slicc method error fix | Brad Beckmann | |
| Added error message when a method call is not supported by an object. | |||
| 2009-11-18 | ruby: slicc action error fix | Brad Beckmann | |
| Small fix to the State Machine error message when duplicate actions are defined. | |||
| 2009-11-18 | ruby: slicc state machine error fixes | Brad Beckmann | |
| Added error messages when: - a state does not exist in a machine's list of known states. - an event does not exist in a machine - the actions of a certain machine have not been declared | |||
| 2009-11-18 | ruby: Removed unused action z_stall | Brad Beckmann | |
| 2009-11-18 | m5: Added option to take a checkpoint at the end of simulation | Brad Beckmann | |
| 2009-11-18 | m5: Fixed bug in atomic cpu destructor | Brad Beckmann | |
| 2009-11-18 | ruby: fixed dma mi example to work with multiple dma ports | Brad Beckmann | |
| 2009-11-18 | m5: removed master and slave deletions. | Brad Beckmann | |
| The unresolved destructor call caused a seg fault when called. | |||
| 2009-11-18 | m5: fixed destructor to deschedule the tickEvent and event | Brad Beckmann | |
| 2009-11-18 | ruby: getPort function fix | Brad Beckmann | |
| Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter | |||
| 2009-11-18 | ruby: Fixed Directory memory destructor | Brad Beckmann | |
| 2009-11-18 | m5: Moved profile option since Simulation depends on it. | Brad Beckmann | |
| 2009-11-18 | m5: Added isValidSrc and isValidDest calls to packet.hh | Brad Beckmann | |
| 2009-11-18 | ruby: included ruby config parameter ports per core | Brad Beckmann | |
| Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port. | |||
| 2009-11-18 | ruby: Added error check for openning the ruby config file | Brad Beckmann | |
| 2009-11-18 | ruby: Support for merging ALPHA_FS and ruby | Brad Beckmann | |
| Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports. | |||
| 2009-11-18 | ruby: Added more info to bridge error message | Brad Beckmann | |
| 2009-11-18 | ruby: Ruby 64-bit address output fixes. | Brad Beckmann | |
| 2009-11-18 | ruby: Ruby destruction fix. | Brad Beckmann | |
| 2009-11-18 | ruby: Ruby debug print fixes. | Brad Beckmann | |
| 2009-11-18 | ruby: Ruby memtest python script. | Brad Beckmann | |
| 2009-11-17 | ARM: Begin implementing CP15 | Ali Saidi | |
| 2009-11-17 | ARM: Differentiate between LDM exception return and LDM user regs. | Ali Saidi | |
| 2009-11-17 | ARM: Boilerplate full-system code. | Ali Saidi | |
| --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh | |||
| 2009-11-16 | imported patch isa_fixes2.diff | Ali Saidi | |
| 2009-11-15 | ARM: Make the exception return form of ldm restore CPSR. | Gabe Black | |
| 2009-11-15 | ARM: Create a new type of load uop that restores spsr into cpsr. | Gabe Black | |
| 2009-11-14 | ARM: Check in the actual change from the last commit. | Gabe Black | |
| The last commit was somehow empty. This was what was supposed to go in it. | |||
| 2009-11-14 | ARM: Switch the immediate and register versions of msr. | Gabe Black | |
| These were accidently transposed. This change straightens them out. | |||
| 2009-11-14 | ARM: Fix up the implmentation of the msr instruction. | Gabe Black | |
| 2009-11-14 | ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. | Gabe Black | |
| 2009-11-14 | ARM: Add a bitfield to indicate if an immediate should be used. | Gabe Black | |
| 2009-11-14 | ARM: Write some functions to write to the CPSR and SPSR for instructions. | Gabe Black | |
| 2009-11-14 | ARM: Fix up the implmentation of the mrs instruction. | Gabe Black | |
| 2009-11-14 | ARM: More accurately describe the effects of using the control operands. | Gabe Black | |
| 2009-11-14 | ARM: Hook up the moded versions of the SPSR. | Gabe Black | |
| These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode. | |||
| 2009-11-14 | SE: Fix SE mode OS X compilation. | Ali Saidi | |
| 2009-11-14 | ARM: Move around decoder to properly decode CP15 | Ali Saidi | |
| 2009-11-11 | X86: add ULL to 1's being shifted in 64-bit values | Vince Weaver | |
| Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base. | |||
| 2009-11-10 | ARM: Fix some bugs in the ISA desc and fill out some instructions. | Gabe Black | |
| 2009-11-10 | Merge with the head. | Gabe Black | |
| 2009-11-10 | Mem: Eliminate the NO_FAULT request flag. | Gabe Black | |
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