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arch/alpha/isa_desc:
Add cache port bindings for mb & wmb.
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extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39
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execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
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extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
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arch/alpha/isa_desc:
Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
Add comment clarifying when branchTarget() can be used
on indirect branches.
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extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
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the ROB (so we know they're correct-path) before we mark them ready to issue.
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multithreading, which has been gone for a long time.
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Eliminate indirect decoder.cc dependence on rob_station.hh via full_cpu.hh.
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This primarily to be internally consistent (sometimes we used one,
sometimes the other, even within the same line of code!).
I picked the latter to be symmetric with "Foo *foo".
base/cprintf_formats.hh:
base/range.hh:
base/refcnt.hh:
base/res_list.hh:
base/statistics.hh:
base/str.hh:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/syscall_emul.hh:
Change "Foo& foo" declarations to "Foo &foo".
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extra : convert_revision : ca1b0e85a578b539214bda3b8d61ac23792f2e87
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Statistics::NodePtr, StaticInstPtr, ethernet PacketPtr.
base/statistics.hh:
Change NodePtr parameters to Nodeptr &.
cpu/exetrace.hh:
Change StaticInstPtr parameters to StaticInstPtr &.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ethertap.hh:
change PacketPtr parameters to PacketPtr &.
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extra : convert_revision : a778efdca33b0ec5beb76cf47db0e9e4728897ee
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This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
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extra : convert_revision : 9e85c0fa0f6c5393dd8e91034a49975628cf825d
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setup-spec script
util/setup-spec:
Made some changes so the information contained in the ini file explains
what the init_param value corresponds to
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message about -j).
Check for, delete, and die on zero-length .d files.
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not while printing out the data. This allows the data
to be dumped more than once.
base/cprintf.hh:
need a destructor
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special console values separately.
dev/alpha_console.cc:
use new console specific input function
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extra : convert_revision : 08997d6115d2aac3a26cac2774b3c3fc0cd76ab0
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sim/universe.cc:
oops. this doesn't exist
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statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
Make most output files use the output directory
base/misc.cc:
send warnings to the outputStream as well
base/trace.cc:
dprintf_stream defaults to cerr
dev/console.cc:
use the output directory for the console output if it exists
dev/etherdump.cc:
dump to the output directory if it exists
sim/builder.cc:
sim/builder.hh:
move constructor and destructor to .cc file
use a function to get the stream that the builder dumps its
output to, and create a separate file in the output directory
if able
sim/main.cc:
statStream -> outputStream
sim/serialize.cc:
dump checkpoints to the output directory if specified
sim/universe.cc:
provide an output stream for simulator output. (This takes place of the
statStream catchall that we had before)
Also provide an optional output directory that multiple simulator output
files can be written to.
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extra : convert_revision : 03abce20edbbf7ec19c9ddd8d69ec8485c383532
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Also, compare real paths to ensure that the links point
to the right place
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base/statistics.cc:
dead code
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arch/alpha/isa_desc:
don't say warn: Warning:
base/misc.cc:
avoid printing two newlines in a row
sim/main.cc:
print out a message just before we enter the event queue
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generate a checkpoint that an m5.debug simulator can use
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the interfaces. This allows new bus models to be used without major hassle. And I thought it was time to change it all again anyways.
cpu/simple_cpu/simple_cpu.cc:
Switch doEvents to doEvents()
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but did not test... however the only thing this
affects in libelf is the header, so I don't expect
any functional problems.
base/loader/elf_object.cc:
Set LIBELF_LINUX to 0 to build on zax.
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extra : convert_revision : d024b33deff6fc8ea6f1d465f76dc8d9d63254ab
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to find and remove stats from the files so we can put less
burden on the python interpreter.
base/statistics.cc:
Manually insert newlines into the python code so that we now have one
stat per line. (Make it so we can use grep -v to remove stats)
test/stattest.cc:
update to reflect changes in how python is accessed
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base/loader/elf_object.cc:
- Use program header instead of section headers for loading.
The old code doesn't work for Alpha/Linux user binaries.
- Deal properly with single-segment ELF executables (e.g. kernels)...
haven't tested this but it looks like it matches the functionality
of the patch the L4::Pistachio guys sent.
- Factor load symbol code into one common function.
- Some formatting to match style conventions.
- Only include libelf stuff in .cc file, not .hh.
base/loader/elf_object.hh:
- Use program header instead of section headers for loading.
The old code doesn't work for Alpha/Linux user binaries.
- Factor load symbol code into one common function.
- Only include libelf stuff in .cc file, not .hh.
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class
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so that we can make the first switch time relative.
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(do_data and do_events). If you use the defaults (false and true respectively) you don't have to change your INI files.
arch/alpha/isa_traits.hh:
Add a constant for the maximum address value called MaxAddr.
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which stats to print
- print out the subname
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