gem5 - gem5

Age	Commit message (Expand)	Author
2013-06-09	ruby: stats: use gem5's stats for cache and memory controllers	Nilay Vaish
2013-06-09	ruby: remove undefined functions in Address class	Nilay Vaish
2013-06-09	stats: allow printing vectors on a single line	Nilay Vaish
2013-06-08	config: add atomic cpu to X86_MESI_CMP_directory build options	Nilay Vaish
2013-06-08	Updating EIO regression reference outputs for new stats.	Steve Reinhardt
2013-06-04	scons: ammend swig warning error to version 2.0.10 as well	Ali Saidi
2013-06-04	dev: Clarify why updates are delayed when the MC14818 is activated	Andreas Sandberg
2013-06-03	arch: Create a method to finalize physical addresses	Andreas Sandberg
2013-06-03	base: Make the Python module loader PEP302 compliant	Andreas Sandberg
2013-06-03	config: Add missing CPUs to --restore-with-cpu	Andreas Sandberg
2013-06-03	kvm: Allow architectures to override the cycle accounting mechanism	Andreas Sandberg
2013-06-03	kvm: Add handling of EAGAIN when creating timers	Andreas Sandberg
2013-06-03	sim: Add debug output when executing pseudo-instructions	Andreas Sandberg
2013-06-03	kvm: Add a call to thread->startup() in startup()	Andreas Sandberg
2013-06-03	dev: Add support for disabling ticking and the divider in MC146818	Andreas Sandberg
2013-06-03	dev: Clean up MC146818 register (A & B) handling	Andreas Sandberg
2013-05-30	stats: Update the stats to reflect bus and memory changes	Andreas Hansson
2013-05-30	mem: More descriptive DRAM config names	Andreas Hansson
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-05-30	cpu: Prune the stale TraceCPU	Andreas Hansson
2013-05-30	cpu: Check that minimum TrafficGen period is less than max period	Sascha Bischoff
2013-05-30	cpu: Fix bug when reading in TrafficGen state transitions	Sascha Bischoff
2013-05-30	cpu: Add request elasticity to the traffic generator	Andreas Hansson
2013-05-30	cpu: Block traffic generator when requests have to retry	Andreas Hansson
2013-05-30	cpu: Move traffic generator sending out of generator states	Andreas Hansson
2013-05-30	cpu: Fold together the StateGraph and the TrafficGen	Andreas Hansson
2013-05-30	mem: Make returning snoop responses occupy response layer	Andreas Hansson
2013-05-30	mem: Make the buses multi layered	Andreas Hansson
2013-05-30	mem: Separate the two snoop response cases in the bus	Andreas Hansson
2013-05-30	mem: Tidy up a few variables in the bus	Andreas Hansson
2013-05-30	mem: Add basic stats to the buses	Uri Wiener
2013-05-30	mem: Use unordered set in bus request tracking	Andreas Hansson
2013-05-30	mem: Check for waiting state in bus draining	Andreas Hansson
2013-05-30	mem: Add a LPDDR3-1600 configuration	Andreas Hansson
2013-05-30	mem: Adapt the LPDDR2 to match a single x32 channel	Andreas Hansson
2013-05-30	mem: Avoid explicitly zeroing the memory backing store	Andreas Hansson
2013-05-30	util: Auto generate the packet proto definitions	Andreas Hansson
2013-05-30	base: Avoid size limitation on protobuf coded streams	Andreas Hansson
2013-05-30	cpu: Make hash struct instead of class to please clang	Andreas Hansson
2013-05-21	ruby: slicc: fix error msg in TypeFieldMemberAST.py	Malek Musleh
2013-05-21	x86, regressions: updates stats	Nilay Vaish
2013-05-21	x86: Squash outstanding walks when instructions are squashed.	Gedare Bloom
2013-05-21	x86: mark instructions for being function call/return	Nilay Vaish
2013-05-21	x86: add op class for int and fp microops in isa description	Nilay Vaish
2013-05-21	stats: updates statistics for ruby regressions	Nilay Vaish
2013-05-21	ruby: moesi hammer: cosmetic changes	Nilay Vaish
2013-05-21	ruby: mesi cmp directory: cosmetic changes	Nilay Vaish