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As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
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This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
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rather than in RubySystem object.
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Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
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The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
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to allow override of global location for regression test binaries.
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Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
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Re-enable it and update it for more modern versions of mercurial.
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checkpoint-aggregator.py was written at UM so I added a UM copyright, agg_se.py was
written at AMD so I added the AMD copyright.
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1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
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This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
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cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
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The arguments were added to the global_sticky_vars Variables object after the
basic help text was generated. As a result, the "actual:" value wouldn't
reflect the arguments to scons and wouldn't really be the "actual" value used
by the build. This change fixes that by updating global_sticky_vars slightly
earlier.
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that the cache can make context-specific decisions within their various tag policy implementations.
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base class.
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definitely made implementing a trace cpu easier this way.
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In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
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The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
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These are all after the existing ones, suggesting they were added after the
original list was created.
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through the IO APIC.
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The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
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Added error message when a symbol is not an instance of a particular expected
type.
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* * *
ruby: Removed primitive .hh includes
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