gem5 - gem5

Age	Commit message (Collapse)	Author
2010-02-28	SmartDict: Make SmartDict an attrdict	Nathan Binkert

2010-02-28	uart: use integer versions of time instead of messing around with floats	Nathan Binkert

2010-02-27	Config: Fix fs.py's call to CacheConfig.config_cache.	Gabe Black

2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert

2010-02-26	isa_parser: Make SCons import the isa_parser	Nathan Binkert
	this is instead of forking a new interpreter
2010-02-26	isa_parser: move the operand map stuff into the ISAParser class.	Nathan Binkert

2010-02-26	isa_parser: move more support functions into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move more stuff into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move the formatMap and exportContext into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: Make stack objects class members instead of globals	Nathan Binkert

2010-02-26	isa_parser: add a debug variable that changes how errors are reported.	Nathan Binkert
	This allows us to get tracebacks in certain cases where they're more useful than our error message.
2010-02-26	isa_parser: Use an exception to flag error	Nathan Binkert
	This allows the error to propagate more easily
2010-02-26	isa_parser: Move more stuff into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move code around to prepare for putting more stuff in the class	Nathan Binkert

2010-02-26	isa_parser: simple fixes, formatting and style	Nathan Binkert

2010-02-26	events: Give EventWrapped a default name and description	Nathan Binkert

2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
	Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.
2010-02-25	stats: update stats for the changes I pushed re: shared cache occupancy	Lisa Hsu

2010-02-24	cache stats: account for writebacks and/or device occupancy in the cache.	Lisa Hsu
	Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
	On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
2010-02-23	stats: this makes some fixes to AverageStat and AverageVector.	Lisa Hsu
	Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that.
2010-02-23	cache: pull CacheSet out of LRU so that other tags can use associative sets.	Lisa Hsu

2010-02-20	BaseDynInst: Preserve the faults returned from read and write.	Timothy M. Jones
	When implementing timing address translations instead of atomic, I forgot to preserve the faults that are returned from the read and write calls. This patch reinstates them.
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
	When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2010-02-12	BaseDynInst: Make the TLB translation timing instead of atomic.	Timothy M. Jones
	This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class.
2010-02-12	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	Timothy M. Jones

2010-02-10	ruby: fixed data block assignment fix	Brad Beckmann
	Fixed data block assignment to not delete if not internally allocated.
2010-02-10	ruby: Initialize sender in MI_example-dir	Brad Beckmann

2010-02-10	ruby: Fixed slicc to initialize the m_is_blocking flag	Brad Beckmann

2010-02-01	ruby: Added FS support to the simple mesh topology	Brad Beckmann
	Added full-system support to the simple mesh toplogy by allowing dma contrllers to be attached to router zero in the network.
2010-02-01	ruby: Set default protocol back to MI_example	Brad Beckmann

2010-01-31	merge	Brad Beckmann

2010-01-31	m5: Added PROTOCOL default for regress fix	Brad Beckmann

2010-01-31	inorder: update hello world mips	Korey Sewell

2010-01-31	inorder: vortex alpha regression	Korey Sewell

2010-01-31	inorder: twolf alpha regression	Korey Sewell

2010-01-31	inorder: update hello world alpha	Korey Sewell

2010-01-31	inorder: double delete inst bug	Korey Sewell
	Make sure that instructions are dereferenced/deleted twice by marking they are on the remove list
2010-01-31	inorder: inst count mgmt	Korey Sewell

2010-01-31	inorder: implement split stores	Korey Sewell

2010-01-31	inorder: implement split loads	Korey Sewell

2010-01-31	inorder: add activity stats	Korey Sewell

2010-01-31	inorder: object cleanup in destructors	Korey Sewell

2010-01-31	inorder: user per-thread dummy insts/reqs	Korey Sewell

2010-01-31	inorder: add execution unit stats	Korey Sewell

2010-01-31	inorder: recvRetry bug fix	Korey Sewell
	- on certain retry requests you can get an assertion failure - fix by allowing the request to literally "Retry" itself if it wasnt successful before, and then block any requests through cache port while waiting for the cache to be made available for access
2010-01-31	inorder-stats: add prereq to basic stat	Korey Sewell
	only show requests processed when the resource is actually in use
2010-01-31	inorder: ctxt switch stats	Korey Sewell
	- m5 line enforcement on use_def.cc,hh
2010-01-31	inorder: pipeline stage stats	Korey Sewell
	add idle/run/utilization stats for each pipeline stage
2010-01-31	inorder: enforce stage bandwidth	Korey Sewell
	each stage keeps track of insts_processed on a per_thread basis but we should be keeping that on a total basis inorder to enforce stage width limits