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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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Author
2015-07-20
mem: misc flags for AMD gpu model
Blake Hechtman
2016-01-17
sim: fix redundant --debug-start help string
Steve Reinhardt
2016-01-17
cpu. arch: add initiateMemRead() to ExecContext interface
Steve Reinhardt
2016-01-17
cpu: remove unnecessary data ptr from O3 internal read() funcs
Steve Reinhardt
2016-01-17
arch: don't call *Timing functions from *Atomic versions
Steve Reinhardt
2016-01-17
arch: get rid of unused LargestRead typedef
Steve Reinhardt
2016-01-17
sim: don't ignore SIG_TRAP
Steve Reinhardt
2016-01-17
stats: update SPARC FS stats
Steve Reinhardt
2016-01-15
dev, arm: Add a platform with support for both aarch32 and aarch64
Andreas Sandberg
2016-01-15
dev, arm: Add support for automatic PCI interrupt routing
Andreas Sandberg
2016-01-11
mem: fix bug in packet access endianness changes
Steve Reinhardt
2016-01-11
scons: Enable -Wextra by default
Andreas Hansson
2016-01-11
ext: Replace gzstream with iostream3 from zlib to avoid LGPL
Andreas Hansson
2016-01-11
configs: Fix inheritance of HMCSystem and cleanup spacing
Andreas Hansson
2016-01-07
config: Updates for distributed gem5 simulations
Gabor Dozsa
2016-01-07
dev: Distributed Ethernet link for distributed gem5 simulations
Gabor Dozsa
2016-01-07
pseudo inst,util: Add optional key to initparam pseudo instruction
Gabor Dozsa
2015-12-31
mem: add CacheVerbose debug flag, filter noisy DPRINTFs
Steve Reinhardt
2015-12-31
mem: Do not rely on the NeedsWritable flag for responses
Andreas Hansson
2015-12-31
mem: Do not allocate space for packet data if not needed
Andreas Hansson
2015-12-31
mem: Do not alter cache block state on uncacheable snoops
Andreas Hansson
2015-12-31
mem: Make cache terminology easier to understand
Andreas Hansson
2015-07-20
ruby: slicc: have a static MachineType
Tony Gutierrez
2015-07-20
ruby: slicc: remove support for single machine, multiple types
Tony Gutierrez
2015-12-30
stats: more updates due to PCI changes
Steve Reinhardt
2015-12-28
tests: update EIO reference outputs
Steve Reinhardt
2015-12-28
mem: Explicitly check MSHR snoops for cases not dealt with
Andreas Hansson
2015-12-28
mem: Remove unused cache squash functionality
Andreas Hansson
2015-12-28
mem: Avoid unecessary checks when creating HardPFReq in cache
Andreas Hansson
2015-12-28
mem: Do not use sender state to track forwarded snoops in cache
Andreas Hansson
2015-12-28
mem: Fix cache sender state handling and add clarification
Andreas Hansson
2015-12-18
arm: remote GDB: rationalize structure of register offsets
Boris Shingarov
2015-12-18
sim: Use the old work item behavior by default
Andreas Sandberg
2015-12-17
configs: Make the default memtest behaviour more complex
Andreas Hansson
2015-12-17
mem: Fix memory allocation bug in deferred snoop handling
Andreas Hansson
2015-12-14
sim: Add an option to forward work items to Python
Andreas Sandberg
2015-07-20
mem: add request types for acquire and release
David Hashe
2015-12-12
stats: bump stats to reflect ruby tester changes
Anthony Gutierrez
2015-12-11
regress: updates required for the compute-gpu patches
Brad Beckmann
2015-07-20
ruby: more flexible ruby tester support
Brad Beckmann
2015-12-10
dev: Add missing SConscript in src/dev/i2c
Andreas Sandberg
2015-12-10
dev: Move storage devices to src/dev/storage/
Andreas Sandberg
2015-12-10
dev: Move network devices to src/dev/net/
Andreas Sandberg
2015-12-10
dev: Move i2c functionality to src/dev/i2c/
Andreas Sandberg
2015-12-10
dev: Move the CopyEngine class to src/dev/pci
Andreas Sandberg
2015-12-10
dev: Move existing PCI device functionality to src/dev/pci
Andreas Sandberg
2015-11-05
sim: Disable gzip compression for writefile pseudo instruction
Sascha Bischoff
2015-07-15
arm: Bootloader fix for v8 over 16 cores
Karthik Sangaiah
2015-09-18
dev, arm: Add gem5 extensions to support more than 8 cores
Karthik Sangaiah
2015-12-09
mem: remove acq/rel cmds from packet and add mem fence req
Tony Gutierrez
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