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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
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Author
2014-05-31
style: eliminate equality tests with true and false
Steve Reinhardt
2014-05-24
stats: changes due to recent o3 patch.
Nilay Vaish
2014-05-23
stats: changes due to o3 cpu and ruby message buffer patches
Nilay Vaish
2014-05-23
ruby: slicc: remove unused ids DNUCA*
Nilay Vaish
2014-05-23
ruby: remove old protocol documentation
Nilay Vaish
2014-05-23
ruby: message buffer: drop dequeue_getDelayCycles()
Nilay Vaish
2014-05-23
cpu: o3: remove stat totalCommittedInsts
Nilay Vaish
2014-05-15
config: remove unecessary assignment of etherlink interfaces
Anthony Gutierrez
2014-05-12
syscall emulation: clean up & comment SyscallReturn
Steve Reinhardt
2014-05-12
tests: update t1000 & pc-switcheroo-full stats
Steve Reinhardt
2014-05-10
tests: update eio ref outputs for new stats
Steve Reinhardt
2014-05-09
stats: Bump stats for the fixes, and mostly DRAM controller changes
Andreas Hansson
2014-05-09
config: Bump DRAM sweep bus speed to match DDR4 config
Andreas Hansson
2014-05-09
tests: Reflect name change in DRAM tests
Andreas Hansson
2014-05-09
mem: Update DDR3 and DDR4 based on datasheets
Andreas Hansson
2014-05-09
mem: Add DRAM cycle time
Andreas Hansson
2014-05-09
mem: Simplify DRAM response scheduling
Andreas Hansson
2014-05-09
mem: Add precharge all (PREA) to the DRAM controller
Andreas Hansson
2014-05-09
mem: Remove printing of DRAM params
Andreas Hansson
2014-05-09
mem: Add tRTP to the DRAM controller
Andreas Hansson
2014-05-09
mem: Merge DRAM latency calculation and bank state update
Andreas Hansson
2014-05-09
mem: Add tWR to DRAM activate and precharge constraints
Andreas Hansson
2014-05-09
mem: Merge DRAM page-management calculations
Andreas Hansson
2014-05-09
mem: Add DRAM power states to the controller
Andreas Hansson
2014-05-09
mem: Ensure DRAM refresh respects timings
Andreas Hansson
2014-05-09
mem: Make DRAM read/write switching less conservative
Andreas Hansson
2014-04-17
arm: Make sure UndefinedInstructions are properly initialized
Ali Saidi
2014-04-17
arm: allow DC instructions by default so SE mode works
Ali Saidi
2014-04-17
sim, arm: implement more of the at variety syscalls
Ali Saidi
2014-05-09
cpu: Useful getters for ActivityRecorder
Andrew Bardsley
2014-05-09
cpu: Add flag name printing to StaticInst
Andrew Bardsley
2014-05-09
cpu: Timebuf const accessors
Andrew Bardsley
2014-05-09
arm: Add branch flags onto macroops
Andrew Bardsley
2014-05-09
cpu: Allow setWhen on trace objects
Andrew Bardsley
2014-05-09
arm: add preliminary ISA splits for ARM arch
Curtis Dunham
2014-05-09
arch: teach ISA parser how to split code across files
Curtis Dunham
2014-05-09
config: Avoid generating a reference to myself for Parent.any
Geoffrey Blake
2014-05-09
arch, arm: Preserve TLB bootUncacheability when switching CPUs
Geoffrey Blake
2014-05-09
cpu: add more instruction mix statistics
Curtis Dunham
2014-05-09
mem: Squash prefetch requests from downstream caches
Mitch Hayenga
2014-05-09
stats: Method stats source
Stephan Diestelhorst
2014-05-09
cpu, arm: Allow the specification of a socket field
Akash Bagdia
2014-05-09
mem: Auto-generate CommMonitor trace file names
Sascha Bischoff
2014-05-09
arm: Panics in miscreg read functions can be tripped by O3 model
Geoffrey Blake
2014-05-09
dev: Set HDLCD default pixel clock for 1080p @ 60Hz
Chris Emmons
2014-05-09
arm: quick hack to allow a greater number of CPUs to a guest OS
Matt Evans
2014-05-09
arm: Add Makefile for aarch64 build of util/m5
Eric Van Hensbergen
2014-05-09
arch: remove inline specifiers on all inst constrs, all ISAs
Curtis Dunham
2014-05-09
arm: cleanup ARM ISA definition
Curtis Dunham
2014-03-19
ext: disable PLY debugging
Curtis Dunham
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