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AgeCommit message (Expand)Author
2012-02-10MESI: Add queues for stalled requestsNilay Vaish
2012-02-10sim/system: initialize the pagePtr variableNilay Vaish
2012-02-10Regressions: Update stats due to O3 CPU changesNilay Vaish
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-02-10SE/FS: Record the system pointer all the time for the simple CPU.Gabe Black
2012-02-09MEM: Remove onRetryList from BusPort and rely on retryListAndreas Hansson
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-02-07m5=>gem5: Make the regression script build gem5.* instead of m5.*Gabe Black
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
2012-02-05Regressions: Fix the regress script when "all" is used.Gabe Black
2012-02-03System: Forgot to qrefresh with my last change.Gabe Black
2012-02-02System: Fix the check which detects running out of physical memory.Gabe Black
2012-02-02Regression: Update the regress script after SE/FS mergeAndreas Hansson
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-31Thread: Use inherited baseCpu rather than cpu in SimpleThreadAndreas Hansson
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30Merge with main repository.Gabe Black
2012-01-30Ruby: Connect system port in Ruby network testAndreas Hansson
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-30MEM: Clean-up of Functional/Virtual/TranslatingPort remnantsAndreas Hansson
2012-01-29Yet another merge with the main repository.Gabe Black
2012-01-29Implement Ali's review feedback.Gabe Black
2012-01-28Config: Enable O3 CPU and Ruby in FS modeNilay Vaish
2012-01-28X86 Regressions: Update stats due to introduction of TSONilay Vaish
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2012-01-28SE/FS: Get rid of the FULL_SYSTEM config option.Gabe Black
2012-01-28SE/FS: Pull FULL_SYSTEM out of the build_opts filesGabe Black
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make both SE and FS tests available all the time.Gabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-28MIPS: Fix a compiler warning from the eret instruction.Gabe Black
2012-01-28Merge with the main repo.Gabe Black
2012-01-27ns_gige: Fix a missing curly brace in if-statementAndreas Hansson
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
2012-01-25stats: Update stats for final tick and memory bandwidth patchesAli Saidi
2012-01-25sim: display final value of curTick in statsAli Saidi
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish