Age | Commit message (Collapse) | Author |
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extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
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src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
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extra : convert_revision : 7276059c798a85cb9d138ccc5531298ecd055c13
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src/mem/bus.cc:
Actually return the snoop list when asked for it.
Don't get stuck in infinite functional loops
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extra : convert_revision : 8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
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src/cpu/simple/atomic.cc:
Make the atomic cpu return 0 on snoops.
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extra : convert_revision : aad96ad36e0c764c7cfef8b0c8e97877574f5845
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extra : convert_revision : 82882eb131aa66eba9f281b64db21d5cbfefb1b9
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extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
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configs/splash2/run.py:
Fix MaxTick for splash configs
configs/splash2/cluster.py:
Add a config that allows clusters of CPU's to be attached to a single L1
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extra : convert_revision : 1bb0a0c5f4889316940a9858be90ae2eaa849f1a
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the Debug param context
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extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
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dependencies/versions/libraries/etc
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : 6ef2249bfa3f7149830efdb42a313422090da7d7
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extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
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extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
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the recent TLB changes. Now PAL mode accesses are counted as hits in the TLB.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
Update refs.
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extra : convert_revision : 6798c5753d4d7bd7b5667d59cf564012b781ce8a
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extra : convert_revision : 05db10e20d33302fe830d5759b8881b1233aca87
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src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
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extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
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extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
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Rename cc_main to internal.main
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extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
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src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
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extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
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configs/example/memtest.py:
configs/splash2/run.py:
Update for maxtick
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extra : convert_revision : 94106625be1ebc2b614db16720a4861e47222c0b
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extra : convert_revision : aa34e0e7254daf20ecb7c14d430f08927a8fb9ca
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 498304c24435437f8f1942bb8aeafe69ba22a089
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check here for responses that match as well
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extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f
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Fixes for Mem Leak associated with Writebacks.
src/mem/cache/miss/mshr_queue.cc:
Fixes for Mem Leak associated with Writebacks. (Double Delete removed)
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extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
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If you get inserted in the front, reschedule the event
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extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
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extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
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src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
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extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
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src/mem/cache/base_cache.cc:
On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
Create a wrapper to toggle the hasData flag on delayed responses
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extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
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extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
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SConscript file instead of basing it on DEBUG
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extra : convert_revision : 6e6807cc4350ef92baeaaabfeb3dc0bb785128ba
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extra : convert_revision : 54e3dfbc1022fcc663a9c0e67f6434395d1fe33c
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the parameters to the BaseCPU object.
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extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
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impression that this code is ISA independent.
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extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
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src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
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extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
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to crash all configs.
Working on that now.
src/mem/cache/base_cache.cc:
Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
Properly put things on a list for responses so we can search the list.
Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
Properly return when the first read hit on a functional access.
Make sure to call to check the other ports list of packets before forwarding it out.
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extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
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write intersections.
src/mem/packet.cc:
Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
Fix for the proper semantics of fixPacket
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extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e4f9bb663099662a94c5522e6b4955c2a83bac8d
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use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
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extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 35e2ff6ce62281299ad98dca64ba04a3a8a6757c
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the virtual address.
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Ctrl_Base_DepTag.
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properly.
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extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
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code to read and write the strand_sts_reg, and made restored a Priv instruction.
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