Age | Commit message (Collapse) | Author |
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operations and the majority of the load & store operations (not all of FP-Ops),
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...
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extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
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shift)
arch/mips/isa/bitfields.def:
Add comment, move definition up in file
arch/mips/isa/decoder.def:
add basic arithmetic operations
arch/mips/isa/formats/fp.format:
change Integer -> FP words
arch/mips/isa/formats/int.format:
Add derived IntImm class
arch/mips/isa/operands.def:
change to MIPS sytle operands
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rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format
rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format
extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
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--HG--
rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def
rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def
rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def
rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def
extra : convert_revision : 45cb5485311d51982ebcaf1c7eec34e8751c31f5
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rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format
extra : convert_revision : 5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde
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arch/mips/isa/formats/fpop.format:
Floating Point Formats
arch/mips/isa/formats/tlb.format:
TLB Ops Format
arch/mips/isa/mips.isa:
Name change to mips.isa
--HG--
rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h
rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h
rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h
rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format
rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format
rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format
rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format
rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format
rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format
rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h
rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h
extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed
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into zeep.eecs.umich.edu:/z/saidi/work/m5.multiarch
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into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
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here, so it has to be defined before the rule to that calls
isa_parser.py
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of tabs so using different editors is consistent
util/emacs/m5-c-style.el:
Default to inserting spaces instead of tabs so using different
editors is consistent
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arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
changing "sparc" strings to "mips" everywhere
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decode it but NOT produce any C++ class object.
All of the code literals are empty as of now. As much as possible instructions were organized into relevant "formats"
and also references to the tables I used from the MIPS manual were noted via appropriate comments.
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extra : convert_revision : 9b44fb40e900061a4cdb290b6a5aaceb9750ae13
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arch/mips/isa_desc/bitfields.h:
Change from table names to actual bitfield name ...
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- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
arch/mips/isa_desc/bitfields.h:
initial bitfield constants ... copied some from original alpha bitfields
arch/mips/isa_desc/decoder.h:
decoder function skeleton pt.1
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
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arch/mips/isa_desc/bitfields.h:
arch/mips/isa_desc/formats.h:
arch/mips/isa_desc/formats/basic.format:
arch/mips/isa_desc/formats/branch.format:
arch/mips/isa_desc/formats/integerop.format:
arch/mips/isa_desc/formats/mem.format:
arch/mips/isa_desc/formats/noop.format:
arch/mips/isa_desc/formats/trap.format:
arch/mips/isa_desc/includes.h:
arch/mips/isa_desc/operands.h:
arch/mips/isa_traits.cc:
arch/mips/isa_traits.hh:
copied from sparc ISA directory
arch/mips/isa_desc/decoder.h:
decoder I started to work on...
--HG--
rename : arch/sparc/isa_desc/bitfields.h => arch/mips/isa_desc/bitfields.h
rename : arch/sparc/isa_desc/decoder.h => arch/mips/isa_desc/decoder.h
rename : arch/sparc/isa_desc/formats.h => arch/mips/isa_desc/formats.h
rename : arch/sparc/isa_desc/formats/basic.format => arch/mips/isa_desc/formats/basic.format
rename : arch/sparc/isa_desc/formats/branch.format => arch/mips/isa_desc/formats/branch.format
rename : arch/sparc/isa_desc/formats/integerop.format => arch/mips/isa_desc/formats/integerop.format
rename : arch/sparc/isa_desc/formats/mem.format => arch/mips/isa_desc/formats/mem.format
rename : arch/sparc/isa_desc/formats/noop.format => arch/mips/isa_desc/formats/noop.format
rename : arch/sparc/isa_desc/formats/trap.format => arch/mips/isa_desc/formats/trap.format
rename : arch/sparc/isa_desc/includes.h => arch/mips/isa_desc/includes.h
rename : arch/sparc/isa_desc/operands.h => arch/mips/isa_desc/operands.h
rename : arch/sparc/isa_traits.cc => arch/mips/isa_traits.cc
rename : arch/sparc/isa_traits.hh => arch/mips/isa_traits.hh
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repository was created.
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
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arch/sparc/isa_desc/bitfields.h:
This file defines the bit fields used by the isa description system
arch/sparc/isa_desc/decoder.h:
This file describes the decoder for the isa description system
arch/sparc/isa_desc/formats.h:
This file declares the instruction formats
arch/sparc/isa_desc/formats/basic.format:
This file implements the "basic" instruction format
arch/sparc/isa_desc/formats/branch.format:
This file implements the "branch" instruction format
arch/sparc/isa_desc/formats/integerop.format:
This file implements the "integerop" instruction format
arch/sparc/isa_desc/formats/mem.format:
This file implements the "mem" instruction format
arch/sparc/isa_desc/formats/noop.format:
This file implements the "noop" instruction format
arch/sparc/isa_desc/formats/trap.format:
This file implements the "trap" instruction format
arch/sparc/isa_desc/includes.h:
This file is all of the inclues that are used by the isa description system
--HG--
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needed in a few more cases.
base/intmath.hh:
align arg to roundUp should be int, not template class
sim/process.cc:
sim/syscall_emul.hh:
No need for explicit template arg now that roundUp is fixed.
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arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
Rename intmath.hh functions to follow m5 style
(RoundUp -> roundUp, etc.).
base/intmath.cc:
Rename intmath.hh functions to follow m5 style
(RoundUp -> roundUp, etc.).
Also reindent code in m5 style.
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operation fails because information is wrong or not available.
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without using the jobfile.
util/stats/db.py:
util/stats/profile.py:
Make it possible to send job as a string and to set the system
separately from the job.
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people won't think they're getting an error when they're not.
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cpu/simple/cpu.cc:
Properly set the Instruction Read bit in the Memory Request
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variable
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dev/pktfifo.hh:
we can't modify i because it's used further down to remove
the packet from the fifo. Instead, copy the iterator and
modify that to get the previous packet.
dev/sinic.cc:
- don't change the transmit state and kick the machine unless
we're at the head of the txList.
- add a couple of debugging statements to figure out how far
along we've gotten in processing a packet.
- assert that the current tx vnic has something to do when
we start processing the state machine.
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from #ifdef DEBUG to #ifndef NDEBUG
base/remote_gdb.cc:
make the remote debugger gdb stuff work in m5.opt
sim/system.cc:
sim/system.hh:
make the console panic break event happen in m5.opt
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separate the rx thread and tx thread and get rid of the dedicated flag.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
dedicated flag goes away, we have new individual flags for
rx thread and tx thread
dev/sinic.cc:
Virtualize sinic
- The io registers are replicated many times in memory, allowing the NIC to
differentiate among several virtual interfaces.
- On the TX side, this allows multiple CPUs to initiate transmits at the same
time without locking in the software. If a partial packet is transmitted,
then the state machine blocks waiting for that virtual interface to complete
its packet. Then the state machine will move on to the next virtual
interface. The commands are kept in fifo order.
- On the RX side, multiple partial transmits can be simultaneously done.
Though a packet does not deallocate its fifo space until all preceeding
packets in the fifo are deallocated. To enable multiple receives, it
is necessary for each virtual nic to keep its own information about its
progress through the state machine.
dev/sinic.hh:
Virtualize sinic
Receive state must be virtualized since we allow the receipt of packets in
parallel.
dev/sinicreg.hh:
Virtualize sinic
separate rx thread and tx thread
create a soft interrupt and add a command to trigger it.
pad out the reserved bits in the RxDone and TxDone regs
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and to remove elements in the middle of the fifo. These elements
do not free space, they are just marked removed. Space is only
freed from the front of the fifo.
dev/etherpkt.cc:
serialize the current slack
dev/etherpkt.hh:
add "slack" to the ethernet packet. It is to be used by any fifo that
the packet is currently in to account for extra space that the packet
may be occupying due to the fifo organization.
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options, making existing options more visible and dealing with
holes in data better.
util/stats/barchart.py:
- move the options for BarChart to a base class ChartOptions so
they can be more easily set and copied.
- add an option to set the chart size (so you can adjust the aspect ratio)
- don't do the add_subplot thing, use add_axes directly so we can
affect the size of the figure itself to make room for the legend
- make the initial array bottom floating point so we don't lose precision
- add an option to set the limits on the y axis
- use a figure legend instead of an axes legend so we can put the legend
outside of the actual chart. Also add an option to set the fontsize of
the legend.
- initial hack at outputting csv files
util/stats/db.py:
don't print out an error when the run is missing from the database
just return None, the error will be print elsewhere.
util/stats/output.py:
- make StatOutput derive from ChartOptions so that it's easier to
set default chart options.
- make the various output functions (graph, display, etc.) take the
name of the data as a parameter instead of making it a parameter to
__init__. This allows me to create the StatOutput object with
generic parameters while still being able to specialize the name
after the fact
- add support for graph_group and graph_bars to be applied to multiple
configuration groups. This results in a cross product of the groups
to be generated and used.
- flush the html file output as we go so that we can load the file
while graphs are still being generated.
- make the proxy a parameter to the graph function so the proper system's
data can be graphed
- for any groups or bars that are completely missing, remove them from
the graph. This way, if we decide not to do a set of runs, there won't
be holes in the data.
- output eps and ps by default in addition to the png.
util/stats/profile.py:
- clean up the data structures that are used to store the function
profile information and try our best to avoid keeping extra data
around that isn't used.
- make get() return None if a job is missing so we know it was
missing rather than the all zeroes thing.
- make the function profile categorization stuff total up to 100%
- Fixup the x-axis and y-axis labels.
- fix the dot file output stuff.
util/stats/stats.py:
support the new options stuff for StatOutput
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on the test system.
add an option for pio_delay_write to run.py
util/stats/stats.py:
full0 -> run0 due to run.py change
sim_ticks doesn't make sense with tick = ps, so use
one of the cpu's numCycles paramter
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increase from 128MB to 512MB
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configs/boot/iscsi-client.rcS:
Clean up the newly updated iscsi-client script.
Reduce the writeback period so writes occur more frequently.
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(apm@brigitte.dna.fi). It provides support for more syscalls in syscall emulation mode.
arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
--HG--
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output for sinic
dev/sinic.cc:
add the cpu number of the request to various panic and trace
output
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dev/ns_gige.cc:
add support for delaying pio writes until the cache access occurs
the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
the txPioRequest and rxPioRequest things were more or less bogus
add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
Add delay_read and delay_write to the register information struct
for now, we won't delay any reads, and we'll delay the writes that
initiate DMAs
python/m5/objects/Ethernet.py:
add a parameter to delay pio writes until the timing access
actually occurs.
--HG--
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--HG--
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--HG--
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--HG--
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pci device base class
dev/sinic.cc:
dev/sinic.hh:
use the new readBar/writeBar stuff that's in the pci device
base class
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makes it easier to implement PCI device models.
dev/pcidev.cc:
default implementations for read/write and readBarX/writeBarX functions
--HG--
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python/m5/config.py:
Clock should not be a NumericParamValue since math on it can be
ambiguous. (As the comment clearly says.)
--HG--
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