Age | Commit message (Collapse) | Author |
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because simple-atomic doesn't seem affected.
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into zeep.pool:/z/saidi/work/m5.newmem
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
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for store conditional.
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extra : convert_revision : 9ecfd5a0a151c03503e42faf98240da12fd719b1
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the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.
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extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
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the script is invoked as main. This allows us to import traceflags.py
if we just want the list of available flags.
Embed traceflags.py into the zipfile so it can be accessed from the
python side of things. With this, print an error on invalid flags and
add --trace-help option that will print out the list of trace flags
that are compiled in. If a flag is prefixed with a '-', now that flag
will be disabled.
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into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/atomic.cc:
merge steve's changes in.
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extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
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conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
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into vm1.(none):/home/stever/bk/newmem-head
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function into Alpha ISA description. write now just generically
returns a result value if the res pointer is non-null (which means
we can only provide a res pointer if we expect a valid result
value).
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used anywhere at all.
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its not all that useful. Fix a few bugs with python/C++
integration.
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We don't currently use randomness much, so I didn't go too far, but
in the future, we may want to actually expose the random number values
themselves to python. For now, I'll at least let you seed it.
While we're at it, clean up a clearly bad way for generating random
doubles.
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access to enabling/disabling tracing. Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.
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that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.) All instances of variadic macros
are not yet removed, but I know how, and it will happen.
One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.
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to a stream compared to sprintf to a buffer.
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
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into zeep.pool:/z/saidi/work/m5.newmem
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
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Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
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Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
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the middle of one
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fix unaligned accesses in mmaped disk device
src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
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directory where tracediff is.
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definition as well as the declaration.
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in debugging mode (especially valuable for tracediff).
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src/arch/sparc/isa/decoder.isa:
fix rdgsr fault check
src/arch/sparc/tlb.cc:
block asis are now supported
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