gem5 - gem5

Age	Commit message (Expand)	Author
2014-03-23	stats: Update stats for DRAM changes	Andreas Hansson
2014-03-23	mem: Track DRAM read/write switching and add hysteresis	Andreas Hansson
2014-03-23	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	Andreas Hansson
2014-03-23	mem: Change memory defaults to be more representative	Andreas Hansson
2014-03-23	mem: Add close adaptive paging policy to DRAM controller model	Wendy Elsasser
2014-03-23	mem: DRAM controller tidying up	Andreas Hansson
2014-03-23	mem: Fix bug in DRAM bytes per activate	Andreas Hansson
2014-03-23	mem: Limit the accesses to a page before forcing a precharge	Andreas Hansson
2014-03-23	mem: Make DRAM write queue draining more aggressive	Andreas Hansson
2014-03-23	config: Add a DRAM efficiency-sweep script	Andreas Hansson
2014-03-23	cpu: DRAM Traffic Generator	Neha Agarwal
2014-03-23	mem: DDR3 config for comparing with DRAMSim2	Neha Agarwal
2014-03-23	mem: More descriptive address-mapping scheme names	Andreas Hansson
2014-03-23	scons: Shush scons	Curtis Dunham
2014-03-23	misc: Fix -q (quiet) flag	Stan Czerniawski
2014-03-23	ruby: Move Ruby debug flags to ruby dir and remove stale options	Andreas Hansson
2014-03-23	util: Add support for detection of gzipped packet traces	Andreas Hansson
2014-03-23	mem: Include the DRAMSim2 wrapper in NULL build	Andreas Hansson
2014-03-23	ext: Fix typo in DRAMSim2 SConscript	Andreas Hansson
2014-03-23	mem: CommMonitor trace warn on non-timing mode	Sascha Bischoff
2014-03-23	cpu: Add basic check to TrafficGen initial state	Stan Czerniawski
2014-03-23	dev: Fix IsaFake's cxx_header setting	Andrew Bardsley
2014-03-23	arm: m5ops readfile64 args broken, offset coming through garbage	Eric Van Hensbergen
2014-03-23	base: Fix error message time unit (cycle -> tick)	Andreas Hansson
2014-03-20	stats: updates due to changes to ruby config scripts	Nilay Vaish
2014-03-20	ruby: consumer: avoid accessing wakeup times when waking up	Nilay Vaish
2014-03-20	ruby: garnet: convert network interfaces into clocked objects	Nilay Vaish
2014-03-20	ruby: slicc: code refactor	Nilay Vaish
2014-03-20	config: ruby: rename _cpu_ruby_ports to _cpu_ports	Nilay Vaish
2014-03-20	config: fs.py: move creating of test/drive systems to functions	Nilay Vaish
2014-03-20	config: remove ruby_fs.py	Nilay Vaish
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-03-17	config: ruby: remove piobus from protocols	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-03-16	kvm: Clean up signal handling	Andreas Sandberg
2014-03-16	kvm: x86: Adjust PC to remove the CS segment base address	Andreas Sandberg
2014-03-16	kvm: x86: Add support for x86 INIT and STARTUP handling	Andreas Sandberg
2014-03-12	alpha: Small removal of dead comments/code from alpha ISA	Paul Rosenfeld
2014-03-07	cpu: Make CPU and ThreadContext getters const	Andreas Hansson
2014-03-07	arm: Handle functional TLB walks properly	Geoffrey Blake
2014-03-07	mem: Fix incorrect assert failure in the Cache	Prakash Ramrakhyani
2014-03-07	mem: Edit proto Packet and enhance the python script	Radhika Jagtap
2014-03-07	scons: Fix clang version identification for OSX	Mitch Hayenga
2014-03-07	misc: Add panic_if / fatal_if / chatty_assert	Stephan Diestelhorst
2014-03-07	scons: Fixes uninitialized warnings issued by clang	Mitch Hayenga
2014-03-07	arm: Fix uninitialised warning with gcc 4.8	Stephan Diestelhorst
2014-03-07	mem: Wakeup sleeping CPUs without caches on LLSC	Ali Saidi
2014-03-06	sim: Schedule the global sync event at curTick() + simQuantum	Andreas Sandberg
2014-03-03	x86: Setup correct TSL/TR segment attributes on INIT	Andreas Sandberg
2014-03-03	kvm: x86: Always assume segments to be usable	Andreas Sandberg