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2018-02-20cpu-o3: Don't add non-speculative mem barriers to the IQ twiceAndreas Sandberg
There are cases where the IEW adds a non-speculative instruction to the IQ twice. This can happen if an instruction is flagged as IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative instructions in the IEW to the IQ by checking if it has been added already. Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-19mem: fix page_table bug for .fast buildBrandon Potter
Since b8b13206c8, the '.fast' build has failed to compile with an error caused by a variable and an assert. As a reminder, assert macros are optimized out of the build for '.fast'. If an assert check requires a variable that is unused anywhere else in the code, the compiler complains that the variable is unused and the scons build fails. The solution is to add a M5_VAR_USED specifier to tell the compiler to ignore the variable. Change-Id: I38f6bbed1e4c0506c5bbc1206c21f1f7e3d8dfe6 Reviewed-on: https://gem5-review.googlesource.com/8462 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-02-19arch-riscv: Fix compressed branch op offsetAlec Roelke
There is a bug in RISC-V's compressed branch instructions where the offsets are not stored in ImmOp's immediate field, causing incorrect branchTarget() return values. This patch adds a new compressed branch op format, CBOp, which correctly stores the offset. Change-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377 Reviewed-on: https://gem5-review.googlesource.com/8441 Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-02-19arch-arm: Semihosting not available in syscall emulationGiacomo Travaglini
Arm Semihosting is not available in syscall emulation since we don't have an Arm system in that scenario. Trying to use it in "se" mode will make getArmSystem assertion fail. Change-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8367 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-19arch-arm: Add support for secure state in semihostingAndreas Sandberg
The semihosting component currently issues non-secure memory accesses using the standard port proxy. This doesn't work when the guest is running in secure state. Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8365 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-19mem: Refactor port proxies to support secure accessesAndreas Sandberg
The current physical port proxy doesn't know how to tag memory accesses as secure. Refactor the class slightly to create a set of methods (readBlobPhys, writeBlobPhys, memsetBlobPhys) that always access physical memory and take a set of Request::Flags as an argument. The new port proxy, SecurePortProxy, uses this interface to issue secure physical accesses. Change-Id: I8232a4b35025be04ec8f91a00f0580266bacb338 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8364 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-19arch-arm: Add aarch64 semihosting supportAndreas Sandberg
Add basic support for Arm Semihosting 2.0 simulation calls [1]. These calls let the guest system call a simulator or debugger to request OS-like support when running bare metal code. With the exception of SYS_SYSTEM, this implementation supports all of the Semihosting 2.0 specification in aarch64. [1] https://developer.arm.com/docs/100863/latest/preface Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8147 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
A new pseudo register has been added to the Misc pool. It is the implementation defined register. This kinds of registers are covered by the architecture and must be treated differently than UNIMPLEMENTED registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the arm arm). Some previously undecoded registers in c9,c10,c11 have now this register type. Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7922 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Arch regs and pseudo regs distinctionGiacomo Travaglini
A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used as a boundary for the number of physical (real) Misc registers in the system. Pseudo registers (like CP15_UNIMPL) have been moved after the NUM_PHYS_MISCREGS identifier, so that their enum number is (NUM_PHYS_MISCREGS < number < NUM_MISCREGS). Moving away those registers has created some free slots that can be used for future Misc register implementation. SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers. This allows us to define as many pseudo registers as we want without being concerned about checkpoint compatibility. Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7921 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix syntax error in TLB::getResultTeChuan Zhu
The patch fixes one syntax error in TLB::getResultTe Change-Id: I31a72a52d5c03f43929a69ca1be61d9c20e76f5b Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix big endian support in {Load,Store}Double64Chuan Zhu
{Load, Store}Double64 didn't consider some of the big-endian situations. Added big-endian related data conversions to correct them. Change-Id: I8840613f94446e6042276779d1f02350ab57987f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8145 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix big endian support in do{Long,L1,L2}DescriptorChuan Zhu
do{Long,L1,L2}Descriptor was not able to load descriptors correctly for big-endian situations, causing recognised Descriptors. Added big-endian related data conversions to correct them. Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8144 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Add support for automatic reset addr selectionAndreas Sandberg
Add an option to automatically set the aarch64 reset vector to the entry point of the kernel. This is useful when running bare metal workloads that don't use a normal boot loader. Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
Changing casting type in src/arch/arm/isa.cc Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8241 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Decode Brk64 instructionsAndreas Sandberg
The brk instruction in aarch64 was decoded as an unimplemented instruction. Fix that. Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16mem: Add PortProxy read/write helper with explicit endiannessAndreas Sandberg
Change-Id: Ia9a11ca68b2892dafd02f2c37324b99b35c77d34 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8146 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-16sim: Add gtoh/htog helpers that take an explicit endiannessChuan Zhu
Add helper functions to swap between guest byte order and host byte order that take a guest endianness as a parameter. These functions are called htog and htog to be consistent with the helper functions that extract guest byte order from a compile time constant. Change-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-16arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64Chuan Zhu
The old code does secure state check by using "el <= EL2", which mis-considers secure EL1 and EL0. This patch fixes this by using inSecureState as in ARM ARM. Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-14mem, sim-se: Fixed seg-fault in EmulationPageTable::remapRico Amslinger
When moving a memory region the target region should be unmapped. The assertion does reflect this, but the following line accesses the invalid pointer regardless. This commit replaces the pointer access with an emplace. Change-Id: I85f9be4e6c223eab447c75043e593ed3f90017e1 Reviewed-on: https://gem5-review.googlesource.com/8261 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-13dev: Remove unused interrupt controller in TerminalAndreas Sandberg
Change-Id: I412d0b5edf2a08217792fa2ed1e511c17d3d31d4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8141 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-13sim: Make Stats truly non-copy-constructibleRekai Gonzalez-Alberquilla
The stats are silently non-copy constructible. Therefore, when someone copy-constructs any object with stats, asserts happen when registering the stats, as they were not constructed in the intended way. This patch solves that by explicitly deleting the copy constructor, trading an obscure run-time assert for a compile-time somehow more meaningful error meassage. This triggers some compilation errors as the FaultStats in the fault definitions of ARM and SPARC use brace-enclosed initialisations in which one of the elements derives from DataWrap, which is not copy-constructible anymore. To fix that, this patch also adds a constructor for the FaultVals in both ISAs. Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-09Fix DDR4_2400_8x8 DRAMCTRL configurationWendy Elsasser
Change-Id: I7af361e146909acc158590354ab22732d4b2f3d5 Signed-off-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8101 Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-09sim: Remove _numContexts member in System classGiacomo Travaglini
A System object has a _numContexts member variable which represent the number of ThreadContext registered in the System. Since this has to match the size of the ThreadContext vector, this patch removes the manually cached size. This was usually used as a for-loop index, whereas we want to enforce the use of range-based loops whenever possible. Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-02-09dev: Fix i8042 device errorsJason Lowe-Power
The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2 for x86) incorrectly added breaks to the i8042 device without implementing the correct functions. This patch implements keyboard writes, but ignores output writes. Information on the PS2 controller can be found at https://wiki.osdev.org/%228042%22_PS/2_Controller Note: Without this patch Linux 4.14 won't boot. Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/7301 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-08mem-cache: Make cache warmup percentage a parameter.Daniel R. Carvalho
The warmupPercentage is the percentage of different tags (based on the cache size) that need to be touched in order to warm up the cache. If Warmup failed (i.e., not enough tags were touched), warmup_cycle = 0. The warmup is not being taken into account to calculate the stats (i.e., stats acquisition starts before cache is warmed up). Maybe in the future this functionality should be added. Change-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e Reviewed-on: https://gem5-review.googlesource.com/8061 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-08arch-arm: Correct SecureMonitorTrap vals for aarch32Giacomo Travaglini
This patch replaces the dummy values which were defined for the SecureMonitorTrap thus enabling its usage in aarch32 mode. 1) It changes the vector table offset from 0x14 to 0x4 in compliance with the armv8 documentation. 2) When trapping in monitor mode for aarch32, the mon_lr is updated with the pc + a non zero offset (+4/2 depending on the current instruction set: +4 for A32, +2 for T32). Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Fixed error in choosing vector offsetChuan Zhu
The old code chose vector offset associated with exceptions taken to EL3 by incorrectly using "from64", which is associated with the exception level where the exception was taken from. However, the offset should depends on the ISA of the lower EL and not of the starting EL itself, as specified in ARM ARM. This patch corrects this by implementing the method in AArch64.TakeException in ARM ARM. Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8001 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
This patch fixes the Illegal Exception return handler. According to the armarm documentation, when PSTATE.IL is set to one because of an illegal exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the Exception level, Execution state, and stack pointer selection do not change as a result of the return. Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8021 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Handle route to EL2 in Supervisor TrapChuan Zhu
Supervisor Trap is supposed to be able to handle exceptions routed to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp() function to Supervisor Trap to handle this, similar to that in UndefinedFault, DataAbort, etc. Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7961 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Change the type of fault for dc ivac instructionsNikos Nikoleris
Change-Id: I00f957a3bc4721a66db62b1257f10e9019a94608 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7829 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Unify permission checks for dc * instructionsNikos Nikoleris
Change-Id: Ib47f4134e3f0a580e5356d384a5d3b293c1af7be Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7828 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Check cache maintenance insts for permission faultsNikos Nikoleris
In AArch32, data cache maintenance instructions that operate by VA do not generate permission faults. In AArch64, a data cache invalidate instruction can generate a permission fault when there are no write permissions to the specified VA. Data cache clean and data cache clean and invalidate instructions do not generate permission faults. Checks for external aborts are also bypassed for data cache maintenance instructions. Change-Id: Iea5bc665e4cf66d528e36b671535b66637c4b224 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7827 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Turn dc ivac to dc civac when some conditions are metNikos Nikoleris
The Arm ARM defines that at EL1 a data cache invalidate instruction performs a data cache clean and invalidate operation if all of the following apply: * EL2 is implemented, * HCR_EL2.VM is set to 1, * SCR_EL3.NS is set to 1 or EL3 is not implemented. This changeset implements this behavior. Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7826 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix printing of the data cache maintenance instructionsNikos Nikoleris
Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7825 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Fix cache line size for cache maintenace instNikos Nikoleris
Cache maintenance operations operate on whole cache blocks. This changeset uses the system cache line size as the size of the cache maintenance requests and masks the lower bits of the effective address. Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7824 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fault when dc ivac is executed from EL0Nikos Nikoleris
A previous change enabled execution of dc ivac from EL0 when SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data cache maintenance operation by VA that cannot be executed from EL0. This changeset essential reverts the change: 8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1 Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7823 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07mem-cache: Only pendingModified MSHRs can satisfy CMO snoopsNikos Nikoleris
We set the satisfied flag when a cache clean request encounters: 1) a block with the dirty bit set, or 2) a pending modified MSHR which means that the cache will get copy of the block that will be soon modified. This changeset fixes a previous bug that set the satisfied flag on snooping MSHR hits even the pendingModified flags was not set. Change-Id: I4968c4820997be5cc1238148eea12a1ba39837d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7822 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-07mem-cache: Cleaned blocks should be marked as not writableNikos Nikoleris
A writeclean packet writes a dirty block to the memory below and therefore sets the dirty flag for the block when the memory below is a cache. If the block was also marked as writable it can satisfy future write requests without further requests/snoops. This can lead to multiple copies of the same block marked as dirty which is not allowed. This changeset clears the writable flag from the cleaned block to prevent the cache from satisfying future write requests without sending a downstream request. Change-Id: I14d3c62fd33f81b1a8ba62374c8565ccab00a6fe Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7821 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
This commit changes the function's name used for retrieving the index of a security banked register given the flatten index. This will avoid confusion with flattenRegId, which has a different purpose. Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix AArch32 SETEND InstructionGiacomo Travaglini
This patch fixes AArch32 SETEND instruction, which was previously executed unconditionally without checking (H)SCTLR.SED field. This bit enables/disables the trapping of the instruction. Change-Id: Ib3d2194c8d16c34ec2a9ab3e8090081900c1e42e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7981 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Correct Illegal Exception Return detectionGiacomo Travaglini
Fixed Illegal Exception Return detection, which was not covering all the documented cases. Change-Id: If08ddc1490d1c0a1fccee1489d116384770ce0a5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7223 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: ELUsingAArch32K from armarm pseudocodeGiacomo Travaglini
This patch implements the ELUsingAArch32K pseudocode, which is returning true if the provided Exception Level is using A32 ISA, but it is not panicking (quitting simulation) if the information is unknown (see documentation). The panicking is the current behaviour of the ELIs32 utility in gem5. Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7222 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: isSecureBelow from armarm pseudocodeGiacomo Travaglini
This patch introduces the inSecureBelow pseudocode function defined in the armarm documentation. It also replaces the inSecureState function call which was improperly used in ELIs32: we might be in secure state (EL3), but with non-secure lower ELs (SCR.NS = 1). Change-Id: I01febcb54392ad4e51e785b4d5153aeb3437c778 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7221 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix incorrect assumptions in ELIs64Chuan Zhu
The state of EL1 wasn't determined correctly when running in secure mode if virtualisation was enabled. This changset updates the implementation to match the canonical behavior from the ARM ARM. Change-Id: I7ed6f5c003617773603f678667aac069d73b6f62 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7141 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-06mem-cache: Remove extra numSets zero check.Daniel R. Carvalho
numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0) is false by definition (and implemmentation*), so there is no need for the double check. * As presented in base/intmath.hh Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9 Reviewed-on: https://gem5-review.googlesource.com/7901 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-06mem: Standardize mem folder header guardsDaniel R. Carvalho
Standardize all header guards in the mem directory according to the most frequent patterns. In general they have the form: mem: __FOLDER_TREE_FILE_NAME_HH__ ruby: __FOLDER_TREE_FILENAME_HH__ Change-Id: I983853e292deb302becf151bf0e970057dc24774 Reviewed-on: https://gem5-review.googlesource.com/7881 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-05base: Update #includes for bitunion.hh.Gabe Black
<iostream> isn't actually used anywhere in bitunion.hh. The templated hash struct type is defined in <functional> and should be included explicitly. Change-Id: I8691ccb2f9e28a01610ae8bb4d9591b07cb7320b Reviewed-on: https://gem5-review.googlesource.com/7781 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
We have not added the --generate-dtb option for non-ARM systems and hence this case becomes dead code. It also leads to error on non-ARM systems as is tries to access a non existent field. Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5 Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/7801 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-05cpu: MinorCPU handling IsSquashAfter flagGiacomo Travaglini
MinorCPU was not handling IsSquashAfter flagged instructions. The behaviour was to force a branch (hence enforcing refetching) for SerializeAfter instructions only. This has now been extended to SquashAfter in order to correctly support ISB barrier instruction behaviour. Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5702 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-05arch-arm: Removing Serializing flag from ISBGiacomo Travaglini
ISB Serializing behaviour is guaranteed by IsSquashAfter, which is inherently serializing; when instruction is commited, consecutive instructions are flushed and refetched. Change-Id: I05e61b4cf9f01113d95b1502c996d04cbd69b759 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5701 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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