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AgeCommit message (Expand)Author
2016-12-05mem: Invalidate a blk when servicing the 1st invalidating targetNikos Nikoleris
2016-12-05mem: Allow non invalidating snoops on an InvalidateReq MSHRNikos Nikoleris
2016-12-05mem: Don't use hasSharers in the snoopFilter for memory responsesNikos Nikoleris
2016-12-05mem: Always use InvalidateReq to service WriteLineReq missesNikos Nikoleris
2016-12-05mem: Assert that the responderHadWritable is set only onceNikos Nikoleris
2016-12-05mem: Ensure InvalidateReq is considered isForward by MSHRsAndreas Hansson
2016-12-05mem: Make packet debug printing more uniformNikos Nikoleris
2016-12-05cpu: Change traffic generators to use different values for writesNikos Nikoleris
2016-12-05mem: Service only the 1st FromCPU MSHR target on ReadRespWithInvNikos Nikoleris
2016-12-05mem: Keep track of allocOnFill in the TargetListNikos Nikoleris
2016-12-05mem: Add support for repopulating the flags of an MSHR TargetListNikos Nikoleris
2016-12-02hsail: disable asserts to allow immediate operands i.e. 0 with loadsBrandon Potter
2016-12-02hsail: add stub type and stub out several instructionsBrandon Potter
2016-12-02hsail: add popcount type and generate popcount instructionsBrandon Potter
2016-12-02hsail: add a wavesize case statement to register operand codeBrandon Potter
2016-12-02hsail: generate mov instructions for more arith_types and bit_typesBrandon Potter
2016-12-02hsail: remove the panic guarding function directivesBrandon Potter
2016-12-02hsail: fix unsigned offset bug in address calculationTony Gutierrez
2016-12-02ruby: Fix overflow reported by ASAN in MessageBuffer.Matthew Poremba
2016-11-30tests: Regression stats updated for recent patchesJason Lowe-Power
2016-11-30riscv: [Patch 8/5] Added some regression tests to RISC-VAlec Roelke
2016-11-30riscv: [Patch 7/5] Corrected LRSC semanticsAlec Roelke
2016-11-30riscv: [Patch 6/5] Improve Linux emulation for RISC-VAlec Roelke
2016-11-30riscv: [Patch 5/5] Added missing support for timing CPU modelsAlec Roelke
2016-11-30riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64AAlec Roelke
2016-11-30riscv: [Patch 3/5] Added RISCV floating point extensions RV64FDAlec Roelke
2016-11-30riscv: [Patch 2/5] Added RISC-V multiply extension RV64MAlec Roelke
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
2016-11-30cpu: Remove branch predictor function predictInOrderJason Lowe-Power
2016-11-30tests: Check for TrafficGen as part of memcheck regressionAndreas Hansson
2016-11-29dev: Fix buffer length when unserializing an eth pktMichael LeBeane
2016-11-28scons: fix sanitizer flags with multiple sanitizersJoe Gross
2016-11-25style: Add options to select checkers and apply fixesAndreas Sandberg
2016-11-25util: git pre-commit hook to check staged filesRekai Gonzalez Alberquilla
2016-11-21ruby: Fix potential bugs in garnet2.0Jieming Yin
2016-11-21gpu-compute: fix segfault when constructing GPUExecContextTony Gutierrez
2016-11-21gpu-compute: init valid field of GpuTlbEntry in default ctorTony Gutierrez
2016-11-21ruby: add default ctor for MachineID typeTony Gutierrez
2016-11-21x86: fix issue with casting in Cvtf2iTony Gutierrez
2016-11-19ruby: init MessageSizeType of SequencerMsg to Request_ControlSooraj Puthoor
2016-11-19x86: fix loading/storing of Float80 typesTony Gutierrez
2016-11-18ext: Update fputils to rev 13589cdAndreas Sandberg
2016-11-17stats, alpha: Update ALPHA statsAndreas Hansson
2016-11-17tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)Andreas Hansson
2016-11-17alpha: Remove ALPHA tru64 support and associated testsAndreas Hansson
2016-10-26hsail,gpu-compute: fixes to appease clang++Tony Gutierrez
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
2016-10-26ruby: Allow multiple outstanding DMA requestsMichael LeBeane
2016-10-26dev: Add 'simLength' parameter in EthPacketDatamlebeane